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型号： MCIMX537CVV8C
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封装： 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件页数： 97/172页
文件大小： 4562K
代理商： MCIMX537CVV8C
i.MX53 Applications Processors for Industrial Products, Rev. 3
30
Freescale Semiconductor
Electrical Characteristics
4.3.2.3
DDR3 Mode I/O DC Parameters
The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. The
parameters in Table 13 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
Differential Input Logic High
Vih(diff)
0.26
See Note2
Differential Input Logic Low
Vil(diff)
See Note2
-0.26
Input current (no pull-up/down)
Iin
Vin = 0 V
Vin=OVDD
—
1
μA
Pull-up/Pull-down impedance Mismatch
-15
+15
%
240 Ohm unit calibration resolution
10
Ohm
Keeper Circuit Resistance
—
1403
—k
Ω
1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
2 The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
3 Use an off-chip pull resistor of less than 60 k
Ω to override this keeper.
Table 13. DDR3 I/O DC Electrical Parameters
Parameters
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage
Voh
—
0.8*OVDD1
1 OVDD – I/O power supply (1.425 V–1.575 V for DDR3)
——
V
Low-level output voltage
Vol
—
0.2*OVDD
V
DC input Logic High
VIH(dc)
—
Vref2+0.1
2 Vref – DDR3 external reference voltage
—OVDD
V
DC input Logic Low
VIL(dc)
—
OVSS
—
Vref-0.1
V
Differential input Logic High
VIH(diff)
—
0.2
—
See Note3
V
Differential input Logic Low
VIL(diff)
—
See Note3
—-0.2
V
Over/undershoot peak
Vpeak
—
0.4
V
Over/undershoot area
(above OVDD or below OVSS)
Varea
—
0.67
V x
nS
Termination Voltage
Vtt
Vtt tracking OVDD/2
0.49*OVDD
Vref
0.51*OVDD
V
Input current (no pull-up/down)
Iin
VI = 0 V
VI=OVDD
—
1
μA
Pull-up/Pull-down impedance mismatch
—
Minimum impedance
configuration
——
3
Ω
240
Ω unit calibration resolution
—
10
Ω
Keeper Circuit Resistance
—
1304
—k
Ω
Table 12. LPDDR2 I/O DC Electrical Parameters1 (continued)
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相关代理商/技术参数
参数描述
MCIMX537CVV8C 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 800 MHZ 529-BGA
MCIMX537CVV8CR2 功能描述:处理器 - 专门应用 iMX53 Rev 2.1 Indust RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432
MCIMX538DZK1C 功能描述:处理器 - 专门应用 I.MX53 2.1 POP RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432
MCIMX53EVK 制造商:Freescale Semiconductor 功能描述:
MCIMX53-LVDS 制造商:Freescale Semiconductor 功能描述:I.MX53 XGA DISPLAY LVDS DEV BOARD 制造商:Freescale Semiconductor 功能描述:I.MX53, XGA DISPLAY, LVDS, DEV BOARD 制造商:Freescale Semiconductor 功能描述:I.MX53, XGA DISPLAY, LVDS CONNECTOR, DEV BOARD; Silicon Manufacturer:Freescale; Core Architecture:ARM; Core Sub-Architecture:Cortex-A8; Silicon Core Number:i.MX5; Silicon Family Name:i.MX53
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