参数资料
型号: MCP14700-E/SN
厂商: Microchip Technology
文件页数: 11/26页
文件大小: 0K
描述: IC MOSFET DRIVER HIGH/LOW 8SOIC
标准包装: 100
配置: 高端和低端,同步
输入类型: 非反相
延迟时间: 27ns
电流 - 峰: 2A
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 36V
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 管件
产品目录页面: 670 (CN2011-ZH PDF)
MCP14700
4.0
4.1
DETAILED DESCRIPTION
Device Overview
When designing with the MCP14700 in applications
where cross conduction of the external MOSFETs is
not desired, care must be taken to ensure the PWM
inputs have the proper timing. There is no internal
The MCP14700 is a synchronous MOSFET driver with
dual independent PWM inputs capable of controlling
cross conduction protection in the MCP14700.
both a ground referenced and floating N-Channel
4.3
Under Voltage Lockout (UVLO)
MOSFET. The PWM input threshold levels are truly
3.0V logic tolerant and have 400 mV of typical
hystereses making the MCP14700 ideal for use with
low voltage controllers.
The MCP14700 is capable of suppling 2A (typical)
peak current to the floating high-side MOSFET that is
connected to the HIGHDR. With the exception of a
capacitor, all of the circuitry needed to drive this
high-side N-channel MOSFET is internal to the
MCP14700. A blocking device is placed between the
The UVLO feature of the MCP14700 does not allow the
HIGHDR or LOWDR output to function when the input
voltage, V CC , is below the UVLO threshold regardless
of the state of the PWM HI and PWM LO pins.
Once V CC reaches the UVLO threshold, the HIGHDR
and LOWDR outputs will respond to the state of the
PWM HI or PWM LO pins. There is a 500 mV hystereses
on the UVLO threshold.
V CC and BOOT pins that allows the bootstrap capacitor
4.4
Overtemperature Protection
to be charged to V CC when the low-side power
MOSFET is conducting. Refer to the application
section, Section 5.1 “Bootstrap Capacitor Select” ,
for information on determining the proper size of the
bootstrap capacitor. The HIGHDR is also capable of
sinking 2A (typical) peak current.
The LOWDR is capable of sourcing 2A (typical) peak
current and sinking 3.5A (typical) peak current. This
helps ensure that the low-side MOSFET stays turned
off during the high dv/dt of the PHASE node.
The MCP14700 is protected from an overtemperature
condition by an internal thermal shutdown feature.
When the internal temperature of the MCP14700
reaches 147°C typically, the HIGHDR and LOWDR
outputs will transition to a low state regardless of the
state of the PWM HI or PWM LO pins. Once the internal
temperature is reduced by 20°C typically, the
MCP14700 will automatically respond to the states of
the PWM HI and PWM LO pins.
4.2
PWM Inputs
4.5 Timing Diagram
The PWM signal applied to the MCP14700 is supplied
A logic high on either PWM pin causes the
corresponding output drive signal to be high. See
by a controller IC. The timing diagram in Figure 4-1
graphically depicts the PWM signal and the output
Figure 4-1
and
Figure 4-2
for a graphical
signals of the MCP14700.
representation of the MCP14700 operation. Internally
the PWM pins are pulled to ground to ensure there is
no drive signal to the external MOSFETs if the pins are
left floating. For reliable operation, it is recommended
that the rising and falling slew rate of the PWM signal
be faster than 1V/50 ns.
PWM LO
t PDHL
t PDLL
LOWDR
t RL
t FL
FIGURE 4-1:
MCP14700 LOWDR Timing Diagram.
? 2009 Microchip Technology Inc.
DS22201A-page 11
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