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| 型号： | MCP1826ST-0802E/DB |
| 厂商： | Microchip Technology |
| 文件页数： | 17/36页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 0.8V 1A SOT223-3 |
| 产品培训模块： | High Current LDOs |
| 标准包装： | 4,000 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 0.8V |
| 输入电压： | 2.3 V ~ 6 V |
| 电压 - 压降（标准）： | 0.25V @ 1A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 1A（最小） |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-261-4，TO-261AA |
| 供应商设备封装： | SOT-223-3 |
| 包装： | 带卷 (TR) |
| 其它名称： | MCP1826ST-0802E/DBTR |
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MCP1826/MCP1826S
4.4
Input Capacitor
Low input source impedance is necessary for the LDO
output to operate properly. When operating from
V PWRGD_TH
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 μF to 4.7 μF is recommended for most
V OUT
T PG
applications.
For applications that
have output step load
V OH
T VDET_PWRGD
requirements, the input capacitance of the LDO is very
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from in order to respond quickly to
the output load step. For good step response
PWRGD
V OL
performance, the input capacitor should be of
equivalent (or higher) value than the output capacitor.
The capacitor should be placed as close to the input of
the LDO, as is practical. Larger input capacitors will
also help reduce any high-frequency noise on the input
and output of the LDO and reduce the effects of any
inductance that exists between the input source
voltage and the input capacitance of the LDO.
4.5 Power Good Output (PWRGD)
The PWRGD output is used to indicate when the output
voltage of the LDO is within 92% (typical value, see
and Maximum specifications) of its nominal regulation
value.
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good threshold plus the hysteresis
value. Once this threshold has been exceeded, the
power good time delay is started (shown as T PG in the
Electrical Characteristics table). The power good time
delay is fixed at 200 μs (typical). After the time delay
period, the PWRGD output will go high, indicating that
the output voltage is stable and within regulation limits.
FIGURE 4-2:
V IN
30 μs
SHDN
V OUT
PWRGD
FIGURE 4-3:
Shutdown.
T OR
70 μs
Power Good Timing.
T PG
Power Good Timing from
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
4.6
Shutdown Input (SHDN)
low. The power good circuitry has a 170 μs delay when
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See Figure 4-2 for power good
timing characteristics.
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low
immediately, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
1.2 mA (V PWRGD < 0.4V maximum).
? 2007 Microchip Technology Inc.
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a
percentage of the input voltage. The typical value of
this shutdown threshold is 30% of V IN , with minimum
and maximum limits over the entire operating
temperature range of 45% and 15%, respectively.
The SHDN input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the shutdown input signal.
On the rising edge of the SHDN input, the shutdown
circuitry has a 30 μs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN input signal. After
DS22057A-page 17
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| MCP1826ST-1202E/DB | 功能描述:低压差稳压器 - LDO 1A CMOS LDO Vout 1.2V ETR RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| MCP1826ST-1202E/EB | 功能描述:低压差稳压器 - LDO 1A CMOS LDO Vout 1.2V ETR RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| MCP1826ST-1802E/DB | 功能描述:低压差稳压器 - LDO 1A CMOS LDO Vout 1.8V ETR RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| MCP1826ST-1802E/EB | 功能描述:低压差稳压器 - LDO 1A CMOS LDO Vout 1.8V ETR RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| MCP1826ST-2502E/DB | 功能描述:低压差稳压器 - LDO 1A CMOS LDO Vout 2.5V ETR RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
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