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| 型号： | MCP2515DM-PTPLS |
| 厂商： | Microchip Technology |
| 文件页数： | 41/92页 |
| 文件大小： | 0K |
| 描述： | BOARD DAUGHTER PICTAIL MCP2515 |
| 标准包装： | 1 |
| 系列： | * |
| 主要目的： | 接口，CAN 控制器 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | MCP2515，MCP2551 |
| 主要属性： | 置于 PICtail Plus 子板内的 CAN 控制器和 CAN 收发器 |
| 已供物品： | 板，CD |
| 产品目录页面： | 685 (CN2011-ZH PDF) |
| 相关产品： | MCP2515T-I/ST-ND - IC CAN CONTROLLER W/SPI 20TSSOP MCP2515T-I/SO-ND - IC CAN CONTROLLER W/SPI 18SOIC MCP2515T-E/ST-ND - IC CAN CONTROLLER W/SPI 20TSSOP MCP2515T-E/SO-ND - IC CAN CONTROLLER W/SPI 18SOIC MCP2515-E/ST-ND - IC CAN CONTROLLER W/SPI 20TSSOP MCP2515-E/SO-ND - IC CAN CONTROLLER W/SPI 18SOIC MCP2515-E/P-ND - IC CAN CONTROLLER W/SPI 18DIP MCP2515-I/ST-ND - IC CAN CONTROLLER W/SPI 20TSSOP MCP2515-I/SO-ND - IC CAN CONTROLLER W/SPI 18SOIC MCP2515-I/P-ND - IC CAN CONTROLLER W/SPI 18DIP 更多... |
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MCP2515
5.2
Synchronization
5.2.2.2
No Phase Error (e = 0 )
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. Synchronization is
If the magnitude of the phase error is less than or equal
to the programmed value of the SJW, the effect of a
resynchronization is the same as that of a hard
synchronization.
the process by which the DPLL function is
implemented.
5.2.2.3
Positive Phase Error (e > 0 )
When an edge in the transmitted data is detected, the
logic will compare the location of the edge to the
expected time (SyncSeg). The circuit will then adjust
If the magnitude of the phase error is larger than the
SJW and, if the phase error is positive, PS1 is
lengthened by an amount equal to the SJW.
the values of PS1 and PS2 as necessary.
5.2.2.4
Negative Phase Error (e < 0 )
There are two mechanisms used for synchronization:
If the magnitude of the phase error is larger than the
1.
2.
Hard synchronization
Resynchronization
resynchronization jump width and the phase error is
negative, PS2 is shortened by an amount equal to the
5.2.1
HARD SYNCHRONIZATION
SJW.
Hard synchronization is only performed when there is a
5.2.3
SYNCHRONIZATION RULES
recessive-to-dominant edge during a BUS IDLE
condition, indicating the start of a message. After hard
synchronization, the bit time counters are restarted with
SyncSeg.
Hard synchronization forces the edge that has
occurred to lie within the synchronization segment of
the restarted bit time. Due to the rules of
synchronization, if a hard synchronization occurs, there
will not be a resynchronization within that bit time.
1.
2.
3.
4.
Only recessive-to-dominant edges will be used
for synchronization.
Only one synchronization within one bit time is
allowed.
An edge will be used for synchronization only if
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
A transmitting node will not resynchronize on a
5.2.2
RESYNCHRONIZATION
positive phase error (e > 0 ).
As a result of resynchronization, PS1 may be
lengthened or PS2 may be shortened. The amount of
lengthening or shortening of the phase buffer segments
has an upper-bound, given by the Synchronization
Jump Width (SJW).
The value of the SJW will be added to PS1 or
subtracted from PS2 (see Figure 5-3 ). The SJW
represents the loop filtering of the DPLL. The SJW is
programmable between 1 TQ and 4 TQ.
5.2.2.1
Phase Errors
The NRZ bit coding method does not encode a clock
into the message. Clocking information will only be
derived from recessive-to-dominant transitions. The
property which states that only a fixed maximum
number of successive bits have the same value (bit-
stuffing) ensures resynchronization to the bit stream
during a frame.
The phase error of an edge is given by the position of
the edge relative to SyncSeg, measured in TQ. The
phase error is defined in magnitude of TQ as follows:
? e = 0 if the edge lies within SYNCSEG
? e > 0 if the edge lies before the SAMPLE POINT
(TQ is added to PS1)
? e < 0 if the edge lies after the SAMPLE POINT of
the previous bit (TQ is subtracted from PS2)
? 2003-2012 Microchip Technology Inc.
5.
If the absolute magnitude of the phase error is
greater than the SJW, the appropriate phase
segment will adjust by an amount equal to the
SJW.
DS21801G-page 41
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MCP2515-E | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:Stand-Alone CAN Controller with SPI Interface |
| MCP2515-E/ML | 制造商:Microchip Technology Inc 功能描述: |
| MCP2515-E/P | 功能描述:网络控制器与处理器 IC W/ SPI Inter 125dC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| MCP2515-E/SO | 功能描述:网络控制器与处理器 IC W/ SPI Inter 125dC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| MCP2515-E/SORB4 | 制造商:Microchip Technology Inc 功能描述: |
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