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| 型号： | MCP2515DM-PTPLS |
| 厂商： | Microchip Technology |
| 文件页数： | 51/92页 |
| 文件大小： | 0K |
| 描述： | BOARD DAUGHTER PICTAIL MCP2515 |
| 标准包装： | 1 |
| 系列： | * |
| 主要目的： | 接口，CAN 控制器 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | MCP2515，MCP2551 |
| 主要属性： | 置于 PICtail Plus 子板内的 CAN 控制器和 CAN 收发器 |
| 已供物品： | 板，CD |
| 产品目录页面： | 685 (CN2011-ZH PDF) |
| 相关产品： | MCP2515T-I/ST-ND - IC CAN CONTROLLER W/SPI 20TSSOP MCP2515T-I/SO-ND - IC CAN CONTROLLER W/SPI 18SOIC MCP2515T-E/ST-ND - IC CAN CONTROLLER W/SPI 20TSSOP MCP2515T-E/SO-ND - IC CAN CONTROLLER W/SPI 18SOIC MCP2515-E/ST-ND - IC CAN CONTROLLER W/SPI 20TSSOP MCP2515-E/SO-ND - IC CAN CONTROLLER W/SPI 18SOIC MCP2515-E/P-ND - IC CAN CONTROLLER W/SPI 18DIP MCP2515-I/ST-ND - IC CAN CONTROLLER W/SPI 20TSSOP MCP2515-I/SO-ND - IC CAN CONTROLLER W/SPI 18SOIC MCP2515-I/P-ND - IC CAN CONTROLLER W/SPI 18DIP 更多... |
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MCP2515
7.0
INTERRUPTS
7.2
Transmit Interrupt
The MCP2515 has eight sources of interrupts. The
CANINTE register contains the individual interrupt
enable bits for each interrupt source. The CANINTF
register contains the corresponding interrupt flag bit for
each interrupt source. When an interrupt occurs, the
INT pin is driven low by the MCP2515 and will remain
low until the interrupt is cleared by the MCU. An
When the transmit interrupt is enabled
(CANINTE.TXnIE = 1 ), an interrupt will be generated on
the INT pin once the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. The CANINTF.TXnIF bit will be set to indicate
the source of the interrupt. The interrupt is cleared by
clearing the TXnIF bit.
interrupt can not be cleared if the respective condition
still prevails.
7.3
Receive Interrupt
It is recommended that the Bit Modify command be
used to reset flag bits in the CANINTF register rather
than normal write operations. This is done to prevent
unintentionally changing a flag that changes during the
Write command, potentially causing an interrupt to be
missed.
It should be noted that the CANINTF flags are
read/write and an interrupt can be generated by the
When the receive interrupt is enabled
(CANINTE.RXnIE = 1 ), an interrupt will be generated
on the INT pin once a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving
the EOF field. The CANINTF.RXnIF bit will be set to
indicate the source of the interrupt. The interrupt is
cleared by clearing the RXnIF bit.
MCU setting any of these bits, provided the associated
CANINTE bit is also set.
7.4
Message Error Interrupt
7.1
Interrupt Code Bits
When an error occurs during the transmission or
reception of a message, the message error flag
The source of a pending interrupt is indicated in the
CANSTAT.ICOD (interrupt code) bits, as indicated in
occur, the INT will remain low until all interrupts have
been reset by the MCU. The CANSTAT.ICOD bits will
(CANINTF.MERRF) will be set and, if the
CANINTE.MERRE bit is set, an interrupt will be
generated on the INT pin. This is intended to be used
to facilitate baud rate determination when used in
conjunction with Listen-Only mode.
reflect the code for the highest priority interrupt that is
currently pending. Interrupts are internally prioritized
7.5
Bus Activity Wake-up Interrupt
such that the lower the ICOD value, the higher the
interrupt priority. Once the highest priority interrupt
condition has been cleared, the code for the next
highest priority interrupt that is pending (if any) will be
reflected by the ICOD bits (see Table 7-1 ). Only those
interrupt sources that have their associated CANINTE
enable bit set will be reflected in the ICOD bits.
When the MCP2515 is in Sleep mode and the bus activity
wake-up interrupt is enabled (CANINTE.WAKIE = 1 ), an
interrupt will be generated on the INT pin and the
CANINTF.WAKIF bit will be set when activity is detected
on the CAN bus. This interrupt causes the MCP2515 to
exit Sleep mode. The interrupt is reset by clearing the
WAKIF bit.
TABLE 7-1:
ICOD<2:0>
000
ICOD<2:0> DECODE
Boolean Expression
ERR?WAK?TX0?TX1?TX2?RX0?RX1
Note:
7.6
The MCP2515 wakes up into Listen-Only
mode.
Error Interrupt
001
010
011
100
ERR
ERR?WAK
ERR?WAK?TX0
ERR?WAK?TX0?TX1
When the error interrupt is enabled
(CANINTE.ERRIE = 1 ), an interrupt is generated on
the INT pin if an overflow condition occurs or if the error
state of the transmitter or receiver has changed. The
Error Flag (EFLG) register will indicate one of the
following conditions.
101
ERR?WAK?TX0?TX1?TX2
7.6.1
RECEIVER OVERFLOW
110
111
Note:
ERR?WAK?TX0?TX1?TX2?RX0
ERR?WAK?TX0?TX1?TX2?RX0?RX1
ERR is associated with CANINTE,ERRIE.
An overflow condition occurs when the MAB has
assembled a valid receive message (the message
meets the criteria of the acceptance filters) and the
receive buffer associated with the filter is not available
for loading of a new message. The associated
EFLG.RXnOVR bit will be set to indicate the overflow
condition. This bit must be cleared by the MCU.
? 2003-2012 Microchip Technology Inc.
DS21801G-page 51
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