参数资料
型号: MCP2515T-I/ML
厂商: Microchip Technology
文件页数: 46/88页
文件大小: 0K
描述: IC CAN CTLR W/SPI 2.0B 20-QFN
标准包装: 1
控制器类型: CAN 接口
接口: SPI 串行
电源电压: 2.7 V ~ 5.5 V
电流 - 电源: 10mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-VFQFN 裸露焊盘
供应商设备封装: 20-QFN 裸露焊盘(4x4)
包装: 标准包装
其它名称: MCP2515T-I/MLDKR
MCP2515
DS21801F-page 50
2010 Microchip Technology Inc.
7.6.2
RECEIVER WARNING
The REC has reached the MCU warning limit of 96.
7.6.3
TRANSMITTER WARNING
The TEC has reached the MCU warning limit of 96.
7.6.4
RECEIVER ERROR-PASSIVE
The REC has exceeded the error-passive limit of 127
and the device has gone to error-passive state.
7.6.5
TRANSMITTER ERROR-PASSIVE
The TEC has exceeded the error-passive limit of 127
and the device has gone to error-passive state.
7.6.6
BUS-OFF
The TEC has exceeded 255 and the device has gone
to bus-off state.
7.7
Interrupt Acknowledge
Interrupts are directly associated with one or more
status flags in the CANINTF register. Interrupts are
pending as long as one of the flags is set. Once an
interrupt flag is set by the device, the flag can not be
reset by the MCU until the interrupt condition is
removed.
REGISTER 7-1:
CANINTE – INTERRUPT ENABLE
(ADDRESS: 2Bh)
R/W-0
MERRE
WAKIE
ERRIE
TX2IE
TX1IE
TX0IE
RX1IE
RX0IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
MERRE: Message Error Interrupt Enable bit
1
= Interrupt on error during message reception or transmission
0
=Disabled
bit 6
WAKIE: Wakeup Interrupt Enable bit
1
= Interrupt on CAN bus activity
0
=Disabled
bit 5
ERRIE: Error Interrupt Enable bit (multiple sources in EFLG register)
1
= Interrupt on EFLG error condition change
0
=Disabled
bit 4
TX2IE: Transmit Buffer 2 Empty Interrupt Enable bit
1
= Interrupt on TXB2 becoming empty
0
=Disabled
bit 3
TX1IE: Transmit Buffer 1 Empty Interrupt Enable bit
1
= Interrupt on TXB1 becoming empty
0
=Disabled
bit 2
TX0IE: Transmit Buffer 0 Empty Interrupt Enable bit
1
= Interrupt on TXB0 becoming empty
0
=Disabled
bit 1
RX1IE: Receive Buffer 1 Full Interrupt Enable bit
1
= Interrupt when message received in RXB1
0
=Disabled
bit 0
RX0IE: Receive Buffer 0 Full Interrupt Enable bit
1
= Interrupt when message received in RXB0
0
=Disabled
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