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| 型号： | MCP3001-I/MS |
| 厂商： | Microchip Technology |
| 文件页数： | 7/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 2.7V 1CH SPI 8MSOP |
| 标准包装： | 100 |
| 位数： | 10 |
| 采样率（每秒）： | 200k |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个伪差分，单极 |
| 产品目录页面： | 672 (CN2011-ZH PDF) |
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2007 Microchip Technology Inc.
DS21293C-page 15
MCP3001
5.0
SERIAL COMMUNICATIONS
Communication with the device is done using a stan-
dard SPI compatible serial interface. Initiating commu-
nication with the MCP3001 begins with the CS going
low. If the device was powered up with the CS pin low,
it must be brought high and back low to initiate commu-
nication. The device will begin to sample the analog
input on the first rising edge after CS goes low. The
sample period will end in the falling edge of the second
clock, at which time the device will output a low null bit.
The next 10 clocks will output the result of the conver-
sion with MSB first, as shown in Figure 5-1. Data is
always output from the device on the falling edge of the
clock. If all 10 data bits have been transmitted and the
device continues to receive clocks while the CS is held
low, the device will output the conversion result LSB
first, as shown in Figure 5-2. If more clocks are pro-
vided to the device while CS is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.
If it is desired, the CS can be raised to end the conver-
sion period at any time during the transmission. Faster
conversion rates can be obtained by using this tech-
nique if not all the bits are captured before starting a
new cycle. Some system designers use this method by
capturing only the highest order 8 bits and ‘throwing
away’ the lower 2 bits.
FIGURE 5-1:
Communication with MCP3001 (MSB first Format).
FIGURE 5-2:
Communication with MCP3001 (LSB first Format).
CS
CLK
D
OUT
t
CYC
Power
Down
t
SUCS
t
SAMPLE
t
CONV
t
DATA**
* After completing the data transfer, if further clocks are applied with CS low, the ADC will output LSB first data,
followed by zeros indefinitely. See Figure below.
** t
DATA: during this time, the bias current and the comparator powers down and the reference input becomes a
high impedance node.
t
CSH
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
HI-Z
NULL
BIT B9
B8
B7 B6
NULL
BIT
CS
CLK
D
OUT
t
CYC
Power Down
t
SUCS
t
SAMPLE
t
CONV
t
DATA**
* After completing the data transfer, if further clocks are applied with CS low, the ADC will output zeros indefi-
nitely.
** t
DATA: during this time, the bias current and the comparator powers down and the reference input becomes a
high impedance node leaving the CLK running to clock out the LSB-first data or zeros.
t
CSH
NULL
BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
HI-Z
B1 B2 B3 B4 B5 B6 B7 B8 B9
HI-Z
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