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| 型号： | MCP3001-I/MS |
| 厂商： | Microchip Technology |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 2.7V 1CH SPI 8MSOP |
| 标准包装： | 100 |
| 位数： | 10 |
| 采样率（每秒）： | 200k |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个伪差分，单极 |
| 产品目录页面： | 672 (CN2011-ZH PDF) |
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MCP3001
DS21293C-page 16
2007 Microchip Technology Inc.
6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3001 with
Microcontroller SPI Ports
With most microcontroller SPI ports, it is required to
clock out eight bits at a time. If this is the case, it will be
necessary to provide more clocks than are required for
the MCP3001. As an example, Figure 6-1 and
Figure 6-2 show how the MCP3001 can be interfaced
to a microcontroller with a standard SPI port. Since the
MCP3001 always clocks data out on the falling edge of
clock, the MCU SPI port must be configured to match
this operation. SPI Mode 0,0 (clock idles low) and SPI
Mode 1,1 (clock idles high) are both compatible with
the MCP3001. Figure 6-1 depicts the operation shown
in SPI Mode 0,0, which requires that the CLK from the
microcontroller idles in the ‘low’ state. As shown in the
diagram, the MSB is clocked out of the ADC on the fall-
ing edge of the third clock pulse. After the first eight
clocks have been sent to the device, the microcontrol-
ler’s receive buffer will contain two unknown bits (the
output is at high impedance for the first two clocks), the
null bit and the highest order five bits of the conversion.
After the second eight clocks have been sent to the
device, the MCU receive register will contain the lowest
order five bits and the B1-B4 bits repeated as the ADC
has begun to shift out LSB first data with the extra
clocks. Typical procedure would then call for the lower
order byte of data to be shifted right by three bits to
remove the extra B1-B4 bits. The B9-B5 bits are then
rotated 3 bits to the right with B7-B5 rotating from the
high order byte to the lower order byte. Easier manipu-
lation of the converted data can be obtained by using
this method.
Figure 6-2 shows SPI Mode 1,1 communication which
requires that the clock idles in the high state. As with
mode 0,0, the ADC outputs data on the falling edge of
the clock and the MCU latches data from the ADC in on
the rising edge of the clock.
FIGURE 6-1:
SPI Communication with the MCP3001 using 8-bit segments (Mode 0,0: SCLK idles low).
FIGURE 6-2:
SPI Communication with the MCP3001 using 8-bit segments (Mode 1,1: SCLK idles high).
CS
CLK
910
11
12
13
14
15
16
D
OUT
NULL
BIT
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
HI-Z
B5
B4
B3
B2
B1
B0
B1
B2
B9
B8
B7
B6
??0
MCU latches data from ADC
Data is clocked out of
ADC on falling edges
on rising edges of SCLK
1
2
34
56
78
HI-Z
B3
LSB first data begins
to come out
B4
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
CS
CLK
9
1011
12
1314
15
16
D
OUT
NULL
BIT
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
HI-Z
B5
B4
B3
B2
B1
B0
B1
B2
B9
B8
B7
B6
??0
MCU latches data from ADC
Data is clocked out of
ADC on falling edges
on rising edges of SCLK
12
3
4
5
6
7
8
B3
LSB first data begins
to come out
HI-Z
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
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