参数资料
型号: MCZ33810EK
厂商: Freescale Semiconductor
文件页数: 13/37页
文件大小: 0K
描述: IC IGNITION INJECTOR 32-SOIC
标准包装: 42
应用: 自动
电流 - 电源: 10mA
电源电压: 4.5 V ~ 36 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-BSOP(0.295",7.50mm 宽)裸露焊盘
供应商设备封装: 32-SOICW 裸露焊盘
包装: 管件
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 32 V, -40 ° C ≤ TC ≤ 125 ° C, and calibrated
timers, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR
= 13 V, TA = 25 ° C.
Characteristic
Symbol
Min
Typ
Max
Unit
GENERAL PURPOSE GATE DRIVER PARAMETERS
Short to Battery Fault Detection Filter Timer Accuracy
VDD = High, Outputs Programmed ON
Programmable from 30 μs to 960 μs in replicating increments
Tolerance of timer after using calibration command
Tolerance of timer before using calibration command
Output OFF Open Circuit Fault Filter Timer
VDD = 5.0 V, Outputs Off
Tolerance of timer before using calibration command
V DS(flt-th)
t (OFF)OC
-10
-35
100
+10
+35
400
%
μs
PWM Frequency 10 Hz to 1.28 kHz Tolerance after using calibration
command
PWM Frequency 10 Hz to 1.28 kHz Tolerance before using calibration
command
PWM FREQ
PWM FREQ
-10%
-35%
10%
35%
Gate Driver Short Fault Duty Cycle
GD SHRT_DC
1.0
3.0
%
SPI DIGITAL INTERFACE
TIMING (14)
Falling Edge of CS to Rising Edge of SCLK
t LEAD
ns
Required Setup Time
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
SI to Rising Edge of SCLK
Required Setup Time
Rising Edge of SCLK to SI
Required Hold Time
t LAG
t SI (SU)
t SI (HOLD)
100
50
16
20
ns
ns
ns
SI, CS, SCLK Signal Rise Time (15)
t R (SI)
5.0
ns
SI, CS, SCLK Signal Fall
Time (16)
t F (SI)
5.0
ns
Time from Falling Edge of CS Low-impedance
(17)
t SO (EN)
55
ns
Time from Rising Edge off CS to SO High-impedance
(18)
t SO (DIS)
55
ns
Time from Falling Edge of SCLK to SO Data Valid
Sequential Transfer Rate
(19)
t VALID
t STR
1.0
25
55
ns
μs
Time required between data transfers
DIGITAL INTERFACE
Calibrated Timer Accuracy
Un-calibrated Timer Accuracy
t TIMER
t TIMER
10
35
%
%
Notes
14.
15.
16.
17.
18.
19.
These parameters are guaranteed by design. Production test equipment uses 1.0 MHz, 5.0 V SPI interface.
This parameter is guaranteed by design, however it is not production tested.
Rise and Fall time of incoming SI, CS and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO pin.
Time required for output states data to be terminated at SO pin.
Time required to obtain valid data out from SO following the fall of SCLK with 200 pF load.
33810
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
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