参数资料
型号: MCZ33903B5EK
厂商: Freescale Semiconductor
文件页数: 67/106页
文件大小: 0K
描述: IC SBC CAN HS 5.0V 32SOIC
标准包装: 42
应用: 系统基础芯片
接口: CAN,LIN
电源电压: 5.5 V ~ 28 V
封装/外壳: 32-BSOP(0.295",7.50mm 宽)裸露焊盘
供应商设备封装: 32-SOICW 裸露焊盘
包装: 管件
安装类型: 表面贴装
Analog Integrated Circuit Device Data
Freescale Semiconductor
63
33903/4/5
SERIAL PERIPHERAL INTERFACE
HIGH LEVEL OVERVIEW
SERIAL PERIPHERAL INTERFACE
HIGH LEVEL OVERVIEW
The device uses a 16 bits SPI, with the following
arrangements:
MOSI, Master Out Slave In bits:
bits 15 and 14 (called C1 and C0) are control bits to
select the SPI operation mode (write control bit to
device register, read back of the control bits, read of
device flag).
bit 13 to 9 (A4 to A0) to select the register address.
bit 8 (P/N) has two functions: parity bit in write mode
(optional, = 0 if not used), Next bit ( = 1) in read mode.
bit 7 to 0 (D7 to D0): control bits
MISO, Master In Slave Out bits:
bits 15 to 8 (S15 to S8) are device status bits
bits 7 to 0 (Do7 to Do0) are either extended device
status bits, device internal control register content or
device flags.
The SPI implementation does not support daisy chain
capability.
Figure 41 is an overview of the SPI implementation.
Figure 41. SPI Overview
Bit 15
Bit 13
Bit 11
Bit 12
Bit 10
Bit 14
Bit 9 Bit 8
C1
A4
A2
C0
Bit 7
Bit 5
Bit 3
Bit 4
Bit 2
Bit 6
Bit 1 Bit 0
D7
D5
D3
D4
D2
D6
D1
D0
control bits
A3
register address
Parity (optional) or
A0
A1
P/N
data
MOSI
S15
S13
S11
S14
Do7
Do5
Do3
Do4
Do2
Do6
Do1
Do0
S12
S9
S10
S8
MISO
Device Status
Extended Device Status, Register Control bits or Device Flags
Next bit = 1
CS
SCLK
MOSI
MISO Tri-state
Tri-state
SPI Wave Form, and Signals Polarity
S15
S14
Do0
C1
C0
D0
SCLK signal is low outside of CS active
CS active low. Must rise at end of 16 clocks,
MOSI and MISO data changed at SCLK rising edge
and sampled at falling edge. Msb first.
MISO tri-state outside of CS active
Don’t Care
for write commands, MOSI bits [15, 14] = [0, 1]
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