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| 型号： | MCZ33927EKR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 12/44页 |
| 文件大小： | 0K |
| 描述： | IC FET PRE-DRIVER 3PH 54-SOIC |
| 标准包装： | 1,000 |
| 配置： | 3 相桥 |
| 输入类型： | 反相和非反相 |
| 延迟时间： | 265ns |
| 电流 - 峰： | 600mA |
| 配置数： | 1 |
| 输出数： | 3 |
| 高端电压 - 最大（自引导启动）： | 75V |
| 电源电压： | 8 V ~ 40 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 54-BSSOP（0.295"，7.50mm 宽）裸露焊盘 |
| 供应商设备封装： | 54-SOICW-EP |
| 包装： | 带卷 (TR) |
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 8.0V ≤ V PWR = V BAT ≤ 40V , -40 ° C ≤ T A ≤ 125 ° C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SUPERVISORY AND CONTROL CIRCUITS
Logic Inputs (Px_LS, Px_HS, EN1, EN2) (27)
V
,
High-Level Input Voltage Threshold
Low-Level Input Voltage Threshold
(26) (27)
Logic Inputs (SI, SCLK, CS )
High-Level Input Voltage Threshold
Low-Level Input Voltage Threshold
V IH
V IL
V IH
V IL
–
0.9
–
0.9
–
–
–
–
2.1
–
2.1
–
V
Input Logic Threshold Hysteresis
(26)
V IHYS
100
250
450
mV
Inputs Px_LS, SI, SCLK, CS , Px_HS, EN1, EN2
Input Pull-Down Current, (Px_LS, SI, SCLK, EN1, EN2)
I INPD
8.0
–
18
μA
0.3 V DD ≤ V IN ≤ V DD
Input Pull-Up Current, (CS, Px_HS) (28)
I INPU
0 ≤ V IN ≤ 0.7 V DD
10
–
25
μA
Input Capacitance
(26)
C IN
–
15
–
pF
0.0 ≤ V IN ≤ 5.5V
RST Threshold (29)
RST Pull-Down Resistance
V TH_RST
R RST
1.0
40
–
60
2.1
85
V
k ?
0.3 V DD ≤ V IN ≤ V DD
Power-ON RST Threshold, (V DD Falling)
SO High-Level Output Voltage
V THRST
V SOH
3.4
0.9 V DD
4.0
–
4.5
–
V
V
I OH = 1.0mA
SO Low-Level Output Voltage
V SOL
–
–
0.1 V DD
V
I OL = 1.0mA
SO Tri-State Leakage Current
I SO_LEAK_T
μA
CS = 0.7 V DD , 0.3 V DD = V SO = 0.7 V DD
-1.0
–
1.0
SO Tri-State Capacitance (26) , (30)
C SO_T
–
15
–
pF
0.0 ≤ V IN ≤ 5.5V
INT High-Level Output Voltage
V OH
0.85 V DD
–
V DD
% VDD
I OH = -500μA
INT Low-Level Output Voltage
V OL
–
–
0.5
V
I OL = 500μA
THERMAL WARNING
Thermal Warning Temperature (26) , (31)
Thermal Hysteresis (26)
T WARN
T HYST
150
8
170
10
185
12
°C
°C
Notes
26. This parameter is guaranteed by design, not production tested.
27. Logic threshold voltages derived relative to a 3.3V 10% system.
28. Pull-Up circuits will not allow back biasing of V DD.
29.
30.
31.
There are two elements in the RST circuit: 1) one generally lower threshold enables the internal regulator; 2) the second removes the
reset from the internal logic.
This parameter applies to the OFF state (tri-stated) condition of SO is guaranteed by design but is not production tested.
The Thermal Warning circuit does not force IC shutdown above this temperature. It is possible to set a bit in the MASK register to
generate an interrupt when overtemperature is detected, and the status bits will always read back the state of the three individual
Thermal Warning circuits in the IC.
33927
Analog Integrated Circuit Device Data
12
Freescale Semiconductor
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相关代理商/技术参数 |
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