参数资料
型号: MCZ33927EKR2
厂商: Freescale Semiconductor
文件页数: 4/44页
文件大小: 0K
描述: IC FET PRE-DRIVER 3PH 54-SOIC
标准包装: 1,000
配置: 3 相桥
输入类型: 反相和非反相
延迟时间: 265ns
电流 - 峰: 600mA
配置数: 1
输出数: 3
高端电压 - 最大(自引导启动): 75V
电源电压: 8 V ~ 40 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 54-BSSOP(0.295",7.50mm 宽)裸露焊盘
供应商设备封装: 54-SOICW-EP
包装: 带卷 (TR)
PIN CONNECTIONS
Table 1. 33927 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 20 .
Pin
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Pin Name
PA_HS
PA_LS
VDD
PB_HS
PB_LS
INT
CS
SI
SCLK
SO
PC_LS
PC_HS
AMP_OUT
AMP_N
AMP_P
OC_OUT
Pin Function
Digital Input
Digital Input
Analog Output
Digital Input
Digital Input
Digital Output
Digital Input
Digital Input
Digital Input
Digital Output
Digital Input
Digital Input
Analog Output
Analog Input
Analog Input
Digital Output
Formal Name
Phase A High-Side
Phase A Low-Side
VDD Regulator
Phase B High-Side
Phase B Low-Side
Interrupt
Chip Select
Serial In
Serial Clock
Serial Out
Phase C Low-Side
Phase C High-Side
Amplifier Output
Amplifier Invert
Amplifier Non-Invert
Overcurrent Out
Definition
Active low input logic signal enables the High-Side Driver for Phase A
Active high input logic signal enables the Low-Side Driver for Phase A
VDD regulator output. Internally generated 5V supply
Active low input logic signal enables the High-Side Driver for Phase B
Active high input logic signal enables the Low-Side Driver for Phase B
Interrupt pin output
Chip Select input. It frames SPI commands and enables SPI port
Input data for SPI port. Clocked on the falling edge of SCLK, MSB first
Clock for SPI port and typically is 3.0 MHz
Output data for SPI port. Tri-state until CS becomes low
Active high input logic signal enables the Low-Side Driver for Phase C
Active low input logic signal enables the High-Side Driver for Phase C
Output of the current-sensing amplifier
Inverting input of the current-sensing amplifier
Non-inverting input of the current-sensing amplifier
Totem pole digital output of the Over-current Comparator
28
OC_TH
Analog Input Overcurrent Threshold Threshold of the overcurrent detector
29
VSS
Ground
Voltage Source Supply Ground reference for logic interface and power supplies
30, 31
GND
Ground
Ground
Substrate and ESD reference, connect to VSS
32
VLS_CAP
Analog Output VLS Regulator Output
Capacitor
VLS Regulator connection for additional output capacitor, providing low
impedance supply source for Low-Side Gate Drive
34
PGNDC
Power Input
Phase C Return
Gate current return for the Low-Side FETs for Phase C gate current
35
PC_LS_G
Power Output Phase C Low-Side Gate Gate drive output for Phase C Low-Side
Drive
36
PC_HS_S
Power Input
Phase C High-Side
Source connection for Phase C High-Side FET
Source
37
PC_HS_G
Power Output
Phase C High-Side
Gate Drive for output Phase C High-Side FET
Gate Drive
38
39
PC_BOOT
PGNDB
Analog Input
Power Input
Phase C Bootstrap
Phase B Return
Bootstrap capacitor for Phase C
Gate current return for the Low-Side FETs for Phase B
40
PB_LS_G
Power Output Phase B Low-Side Gate Gate Drive for output Phase B Low-Side
Drive
41
PB_HS_S
Power Input
Phase B High-side
Source connection for Phase B High-Side FET
Source
42
PB_HS_G
Power Output
Phase B High-Side
Gate Drive for output Phase B High-Side
Gate Drive
43
44
PB_BOOT
PGNDA
Analog Input
Power Input
Phase B Bootstrap
Phase A Return
Bootstrap capacitor for Phase B
Gate current return for the Low-Side FETs for Phase A
45
PA_LS_G
Power Output Phase A Low-Side Gate Gate Drive for output Phase A Low-Side
Drive
33927
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
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