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参数资料
型号： MD5764802
厂商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 8M×8 Dynamic RAM(8M×8动态RAM)
中文描述： 8米× 8动态RAM（8米× 8动态内存）
文件页数： 13/45页
文件大小： 613K
代理商： MD5764802
Semiconductor
MSM5716C50/MSM5718C50/MD5764802
13/45
DATA TRANSFER PACKETS
The next set of packet types are used for data transfer. Their formats are summarized in Figure 7.
As in the REQ packet, eight bits are transferred on each wire during each t
PACKET
interval. The rising
and falling edges of the RDRAM clock define the transfer windows for each of these bits. The data
transfer packets will align to the t
PACKET
intervals defined by the START bit of the REQ packet by
simply observing the timing rules that are developed in the next few sections of this document.
DIN and DOUT Packets
There are nine wires allocated for the data bytes. These wires are labeled DQ8..DQ0. The eight bytes
transferred in a DIN or DOUT packet have 72 bits, which are labeled D0..D63 (on the DQ0..DQ7
wires) and E0..E7 (on the DQ8 wire). The 18Mbit RDRAM have storage cells for the E0..E7 bits. The
E0..E7 bits are also used with byte masking operations. This is described in the section on byte
masking on page 22.
COL Packet
The column address A10..A3 of the first octbyte of data (DINa or DOUTa) is provided in the REQ
packet. The COL packet contains an eight bit field A10..A3, which provides the column address for
the second and subsequent data octbytes. The COL packets have a fixed timing relationship with
respect to the DIN and DOUT packets to which they correspond. As the DIN and DOUT packets are
moved (to accommodate interleaving ). the COL packets move with them.
RSTRB and RTERM Packets
The RSTRB and RTERM packets indicate the beginning and end of the DOUT packets that are
transferred during a read transaction. The RSTRB and RTERM packets are each eight bits and consist
of a single “1” in an odd t
CYCLE
position, with the other seven positions “0”. Note that when a
transaction transfers a single data octbyte, the RSTRB and RTERM packets will overlay one another.
This is permitted and is in fact the reason that each packet consists of a single asserted bit. An example
of this case is shown in Figure 14 (a). There will be transaction situations in which the RTERM
overlays a REQ packet (two octbyte interleaved transaction). Again, this is permitted. The general
rule is that the RTERM may overlay any of the other packets on the Command (BUSCTRL) wire, and
RSTRB may overlay any other except for a REQ packet.
WSTRB and WTERM Packets
The WSTRB and WTERM packets indicate the beginning and end of the series of DIN packets that
are transferred during a write transaction. The WSTRB and WTERM packets are each eight bits and
consist of a single “1” in an odd t
CYCLE
position, with the other seven positions “0”. Note that when
a transaction transfers a single data octbyte, the WSTRB and WTERM packets will not overlay one
another (unlike the case of a one octbyte read). An example of this case is shown in Figure 14 (b). There
will be transaction situations in which the WSTRB overlays a REQ packet (no bank activate). Again,
this is permitted. An example of this is shown in Figure 9 (a). The general rule is that the WSTRB may
overlay any of the other packets on the Command (BUSCTRL) wire, and WTERM may overlay any
other except for a REQ packet.
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