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参数资料
| 型号： | MD5764802 |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 8M×8 Dynamic RAM(8M×8动态RAM) |
| 中文描述： | 8米× 8动态RAM（8米× 8动态内存） |
| 文件页数： | 16/45页 |
| 文件大小： | 613K |
| 代理商： | MD5764802 |
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Semiconductor
MSM5716C50/MSM5718C50/MD5764802
16/45
READ TRANSACTIONS
When a controller issues a read request to an RDRAM, one of three transaction cases will occur. This
is a function of the request address and the state of the RDRAM .
READ:
The first case is shown in Figure 8 (a). This occurs when the requested bank has been left in
an activated state and the requested row address matches the address of this activated row. This is
also called a page hit read and is invoked by the READ or READA commands.
There are three timing parameters which specify the positioning of the packets which control the data
transfer. These are as follows:
t
SDR
t
CDR
t
TDR
Start of RSTRB to start of DOUT
Start of COL to start of DOUT
Start of RTERM to end of DOUT
These parameters are all expressed in units of t
CYCLE
, and the minimum and maximum values are
the same; the RSTRB, RTERM, COL, and DOUT packets move together as a block.
A fourth parameter has a minimum value only, and positions the block of data transfer packets
relative to the REQ (address transfer) packet:
t
RSR
Start of REQ to start of RSTRB for READ
When a read transaction is formed, these packet constraints must be observed. In addition, there are
constraints upon the timing of the bank operations which must also be observed. These are shown
in Figure 8 (a) next to the label “Bank Operation”. After the transfer of the REQ packet in T
0
, the
RDRAM performs a column access (requiring t
CAC
for the column access time) of the first data
octbyte DOUTa during T
1
and T
2
. The RDRAM performs three column cycles (requiring t
CC
for the
column cycle time) in order to access the next three data octbytes (DOUTb. DOUTc, DOUTd) during
T
3
, T
4
and T
5
. Each data octbyte is transferred one t
PACKET
interval after it is accessed.
ACTV/READ:
The second case is shown in Figure 8 (b). This occurs when the requested bank has
been left in a precharged state. This is invoked by the ACTV/READ and ACTV/READA commands.
The RSTRB, RTERM, COL, and DOUT packets remain in the same relative positions as in the READ
case, but they move further from the REQ packet:
t
ASR
Start of REQ to start of RSTRB for ACTV/READ
After the transfer of the REQ packet in T
0
, the RDRAM performs an activation operation (requiring
t
RCD
for the row-column delay) during T
1
and T
2
. This leaves the requested row activated. From this
point the sequence of bank operations are identical to the READ case, except that everything has
shifted two t
PACKET
intervals further from the REQ packet. The sum of t
RCD
and t
CAC
is also known
as t
RAC
(the row access time).
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相关代理商/技术参数 |
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|---|---|
| MD-577G/2 | 制造商:Oshino Lamps 功能描述: |
| MD-577G/3 | 制造商:Oshino Lamps 功能描述: |
| MD-577R/2 | 制造商:Oshino Lamps 功能描述: |
| MD-577R/3 | 制造商:Oshino Lamps 功能描述: |
| MD-577Y/2 | 制造商:Oshino Lamps 功能描述: |
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