参数资料
型号: MD83C154CXXX-16P883D
厂商: TEMIC SEMICONDUCTORS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40
文件页数: 74/242页
文件大小: 61013K
代理商: MD83C154CXXX-16P883D
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页当前第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页第205页第206页第207页第208页第209页第210页第211页第212页第213页第214页第215页第216页第217页第218页第219页第220页第221页第222页第223页第224页第225页第226页第227页第228页第229页第230页第231页第232页第233页第234页第235页第236页第237页第238页第239页第240页第241页第242页
165
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recovery logic is
synchronized and the data recovery can begin. The synchronization process is repeated for each start bit.
20.8.2
Asynchronous Data Recovery
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data recovery unit uses a
state machine that has 16 states for each bit in Normal mode and eight states for each bit in Double Speed mode.
Figure 20-6 on page 165 shows the sampling of the data bits and the parity bit. Each of the samples is given a
number that is equal to the state of the recovery unit.
Figure 20-6. Sampling of Data and Parity Bit
The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three
samples in the center of the received bit. The center samples are emphasized on the figure by having the sample
number inside boxes. The majority voting process is done as follows: If two or all three samples have high levels,
the received bit is registered to be a logic 1. If two or all three samples have low levels, the received bit is regis-
tered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxD pin.
The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the
Receiver only uses the first stop bit of a frame.
Figure 20-7 on page 165 shows the sampling of the stop bit and the earliest possible beginning of the start bit of
the next frame.
Figure 20-7. Stop Bit Sampling and Next Start Bit Sampling.
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to
have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for
majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in Figure 20-7 on
page 165. For Double Speed mode the first low level must be delayed to (B). (C) marks a stop bit of full length. The
early start bit detection influences the operational range of the Receiver.
20.8.3
Asynchronous Operational Range
The operational range of the Receiver is dependent on the mismatch between the received bit rate and the inter-
nally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or the internally
generated baud rate of the Receiver does not have a similar (see Table 20-2 on page 166) base frequency, the
Receiver will not be able to synchronize the frames to the start bit.
12
34
56
7
8
9
10
11
12
13
14
15
16
1
BIT n
123
4
5
678
1
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
12
34
56
7
8
9
10
0/1
STOP 1
123
4
5
6
0/1
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
(A)
(B)
(C)
相关PDF资料
PDF描述
MR83C154CXXX-L16P883 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
MR83C154TXXX-L16P883D 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
MQ83C154XXX-20/883 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44
MR80C154-25/883D 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44
MQ83C154XXX-30P883D 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQFP44
相关代理商/技术参数
参数描述
MD83C154-L16 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller
MD83C154T-12 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller
MD83C154T-16 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller
MD83C154T-20 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller
MD83C154T-25 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller