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| 型号： | MIC2124YMM |
| 厂商： | Micrel Inc |
| 文件页数： | 17/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 10-MSOP |
| 产品培训模块： | MIC2124 Synchronous Current Mode DC-DC Buck Controller |
| 标准包装： | 100 |
| 系列： | Hyper Speed Control™ |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 360kHz |
| 占空比： | 93% |
| 电源电压： | 3 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 包装： | 管件 |
| 其它名称： | 576-3639-5 MIC2124YMM-ND |
Micrel, Inc.
PCB Layout Guideline
Warning!!! To minimize EMI and output noise, follow
these layout recommendations.
PCB Layout is critical to achieve reliable, stable and
efficient performance. A ground plane is required to
control EMI and minimize the inductance in power,
signal and return paths.
Inductor
? Keep the inductor connection to the switch node
(LX) short.
? Do not route any digital lines underneath or close to
the inductor.
? Keep the switch node (LX) away from the feedback
(FB) pin.
MIC2124
The following guidelines should be followed to insure
proper operation of the MIC2124 converter.
IC
?
The LX pin should be connected directly to the drain
of the low-side MOSFET to accurate sense the
voltage across the low-side MOSFET.
?
The 2.2μF ceramic capacitor, which connects to the
V IN terminal, must be located right at the IC. The V IN
terminal is very noise sensitive and placement of the
? To minimize noise, place a ground plane underneath
the inductor.
Output Capacitor
capacitor is very critical. Use wide traces to connect
to the IN and PGND pins.
?
Use a wide trace to connect the output capacitor
ground terminal to the input capacitor ground
?
Place the IC and MOSFETs close to the point of
terminal.
load (POL).
?
Phase margin will change as the output capacitor
? Use fat traces to route the input and output power
lines.
? Signal and power grounds should be kept separate
and connected at only one location.
Input Capacitor
? Place the HSD input capacitor next.
? Place the HSD input capacitors on the same side of
the board and as close to the MOSFETs and the IC
as possible.
? Keep both the HSD and PGND connections short.
? Place several vias to the ground plane close to the
HSD input capacitor ground terminal.
value and ESR changes. Contact the factory if the
output capacitor is different from what is shown in
the BOM.
? The feedback trace should be separate from the
power trace and connected as close as possible to
the output capacitor. Sensing a long high current
load trace can degrade the DC load regulation.
Schottky Diode (Optional)
? Place the Schottky diode on the same side of the
board as the MOSFETs and HSD input capacitor.
? The connection from the Schottky diode’s Anode to
the input capacitors ground terminal must be as
short as possible.
?
Use either X7R or X5R dielectric input capacitors.
Do not use Y5V or Z5U type capacitors.
?
The diode’s Cathode connection to the switch node
(LX) must be kept as short as possible.
?
?
?
?
?
Do not replace the ceramic input capacitor with any
other type of capacitor. Any type of capacitor can be
placed in parallel with the input capacitor.
If a Tantalum input capacitor is placed in parallel
with the input capacitor, it must be recommended for
switching regulator applications and the operating
voltage must be de-rated by 50%.
In “Hot-Plug” applications, a Tantalum or Electrolytic
bypass capacitor must be used to limit the over-
voltage spike seen on the input supply with power is
suddenly applied.
An additional Tantalum or Electrolytic bypass input
capacitor of 22uF or higher is required at the input
power connection.
The 2.2μF, which connect to the V IN terminal, must
be located right at the IC. The V IN terminal is very
noise sensitive and placement of the capacitor is
very critical. Connections must be made with wide
trace.
RC Snubber
? Place the RC snubber on the same side of the board
and as close to the MOSFETs as possible.
MOSFETS
? Low-side MOSFET gate drive trace (DL pin to
MOSFET gate pin) must be short and routed over a
ground plane. The ground plane should be the
connection between the MOSFET source and
PGND.
? Chose a low-side MOSFET with a high C GS /C GD ratio
and a low internal gate resistance to minimize the
effect of dv/dt inducted turn-on.
? Do not put a resistor between the LSD output and
the gate.
? Use a 4.5V V GS rated MOSFET. Its higher gate
threshold voltage is more immune to glitches than a
2.5V or 3.3V rated MOSFET. MOSFETs that are
rated for operation at less than 4.5V V GS should not
be used.
June 2010
17
M9999-060810-D
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