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参数资料
| 型号： | MIC2155YML TR |
| 厂商： | Micrel Inc |
| 文件页数： | 13/35页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32MLF |
| 特色产品： | MIC2155/6 Buck Control IC |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 550kHz |
| 占空比： | 80% |
| 电源电压： | 4.5 V ~ 14.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘，32-MLF? |
| 包装： | 标准包装 |
| 产品目录页面： | 1091 (CN2011-ZH PDF) |
| 其它名称： | 576-3527-6 |
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t d =
Micrel, Inc.
VEN1/2
Slope = I SS /C SS
VSS
V OUT
Figure 3. Soft Start Waveforms
Figure 4. Soft Start Circuit
The output voltage starts to rise when V SS is
approximately 1 diode drop above ground, 0.6V.
The startup delay and output voltage risetime can be
approximated using the formula shown below:
Delay
C SS × 0.6V
I SS
MIC2155/2156
Enable
There is an enable pin for each of the two channels.
Asserting EN1 will enable Channel 1 gate drive and
release the soft start circuit. De-asserting EN1 will
disable the gate drive, discharge C SS and disable V DD . It
will bring the controller into a low current off state.
Enable 2 only controls switching of Channel 2. Disabling
Channel 2 stops the switching of the power FETs on
Channel 2 which reduces the V DD current draw. This can
improve efficiency when operating at low output current,
especially when large MOSFETs are used.
Supply Voltages and Internal References
The MIC2155/6 is powered from a 4.5V to 14.5V supply.
The two input supply pins (VIN1 and VIN2) are
connected together in most applications. They are
powered separately in configurations with two input
supply voltages.
VIN1 supplies an internal LDO, which generates the
VDD supply voltage. V DD is used to power the gate drive
circuitry and must be externally decoupled to the power
ground pins (PGND1 and PGND2). A 10μF Ceramic
capacitor is recommended for most applications. The
AVDD pin is the supply pin for the Bandgap reference
and internal analog circuits. A small RC filter
(10 ? /0.1μF) connected to AVDD is recommended to
help attenuate switching noise from the VDD supply.
The dropout of the internal VDD regulator causes VDD
to drop if VIN1 is below 6V. When operating below 6V,
VDD may be jumpered to VIN1. This bypasses the
internal LDO and prevents VDD from dropping out.
An LDO or simple series pass regulator can be used to
limit the VDD voltage for applications with an input
voltage that spans above and below the 6V maximum
V DD limit. Figures 5 and 6 illustrate two examples of
regulating VDD with external circuitry.
C SS × V OUT
14 × I SS
Risetime
t R =
C IN
1μF
C VDD
10μF
C BST
The soft start pin is discharged under the following
conditions:
?
?
?
EN1 pin de-asserted
UVLO on the VIN1 or VDD pins
Overcurrent
?
Overvoltage (latched off)
Figure 5. LDO Regulator
November 2009
13
M9999-111209-B
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