参数资料
型号: MIC2310-1ZTS TR
厂商: Micrel Inc
文件页数: 14/34页
文件大小: 473K
描述: IC HOT SWAP CTLR 2CHAN 24TSSOP
标准包装: 2,500
类型: 热交换控制器
应用: 通用
内部开关:
电流限制: 可调
电源电压: 10.8 V ~ 13.2 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 带卷 (TR)
Micrel, Inc.
MIC2310
 
 
July 2008 
14
M9999-070108-A
 
Primary Overcurrent (OC) Detector Trips Circuit
Breaker and Asserts I_FLT
Figure 3 below illustrates the behavior of the controller
to an OC event after the primary and secondary OC
detection   circuits   have   been   armed   (upon   the
application of an ENABLE LOW-to-HIGH transition
and after t
POR
) and steady-state operation has been
achieved. Note that the assertion of the controllers
PWRGD digital output occurs when the output load
voltage profile is higher than the controllers V
PGH
 
threshold   voltage   and   the   V
GS
   of   the   external
MOSFET is higher than the controllers V
GSPGH
 
threshold voltage.
The use of an external C
PRIMARY
  capacitor sets the
response time, t
POC
, of the primary OC detector
according to the internal V
PRIL
 threshold voltage and
the CPRIMARY pin discharging current, I
PRI
, where
t
POC
  = t
POCSENSE
  + C
PRIMARY
   (V
PRIL
/I
PRI
). Prior to
triggering   the   primary   OC   detector   (i.e.,   when
V
VCCSENSE
-V
SENSE
  < V
CBP
), a 3mA current source is
enabled to hold the CPRIMARY pin voltage to the
internally-generated V
REG
 voltage. When the primary
OC detector has been triggered, the 3mA current
source is first disabled and a 3礎 current sink is
enabled to discharge the external C
PRIMARY
. When
C
PRIMARY
 has discharged below V
PRIL
, a default timer is
enabled. Once the default timer (t
POCSENSE
) times out,
the circuit breaker is tripped, the 3礎 current sink is
disabled, and the 3mA current source is enabled to
discharge C
PRIMARY
 back to V
REG
 quickly. Concurrently,
the GATE drive circuit is disabled and a higher
current, fault-mode pull-down current sink is enabled
at the GATE pin. The DISCH output goes high to
(optionally) drive external pull-down circuitry.
In the event that the CPRIMARY pin is left NC
(intentionally or otherwise), the overcurrent timer
default value is t
POCSENSE
 (250祍 typical), as specified
in the ac specification table. Once the circuit breaker
is latched, the I_FLT digital output is asserted and the
PWRGD digital output becomes de-asserted when the
output voltage profile falls below the controllers V
PGL
 
threshold voltage or the V
GS
 of the external MOSFET
falls below the controllers V
GSPGH
 threshold voltage.
 
t
POC
 = f(C
PRIMARY
)
V
CC
ENABLE
GATE
V
OUT
V
VCCSENSE
 V
SENSE
I_FLT
PWRGD
Power
Good
Power
Not Good
0V
Primary &
Secondary OC
Detectors Armed
t
POC
V
CBS
V
CBP
I_FLT is asserted by Primary OC
Dtector CB Trip after t
POC
+12V, nominal
V
VREG(UVLOH)
 = +4.25V
V
REG
 = 5V, nominal
V
GSPGH
V
GSPGH
V
PGL
t
POR
 
Figure 3. Primary OC Detector Trips Circuit Breaker
 
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