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| 型号： | MIC2310-1ZTS TR |
| 厂商： | Micrel Inc |
| 文件页数： | 17/34页 |
| 文件大小： | 473K |
| 描述： | IC HOT SWAP CTLR 2CHAN 24TSSOP |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电流限制： | 可调 |
| 电源电压： | 10.8 V ~ 13.2 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
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Micrel, Inc.
MIC2310
July 2008
17
M9999-070108-A
Primary OC Trips Circuit Breaker (CB) and CB
Resets with C
RETRY
(Auto-Retry Timing Capacitor)
Figure 6 illustrates the behavior of the controller to a
primary OC event when a C
RETRY
capacitor is used to
automatically reset the circuit breaker. The automatic
reset operation is the same for the case of a
secondary OC event. In this example, the primary and
secondary OC detection circuits have been armed
(upon the application of an ENABLE LOW-to-HIGH
transition and after t
POR
) and the load capacitor is
charged at a controlled dI
D
/dt rate. Note that in this
diagram, ENABLE is tied to V
CC
and rises with V
CC
.
Steady-state operation is achieved as the controllers
PWRGD digital output is asserted when the output
load voltage profile is higher than the controllers V
PGH
threshold voltage and the V
GS
of the external
MOSFET is higher than the controllers V
GSPGH
threshold voltage.
When the primary OC detector has been triggered by
an output current exceeding I
POC
for a time t
POC
, the
circuit breaker is tripped, the GATE drive circuit is
disabled, the fault-mode pull-down current sink is
enabled at the GATE pin, the DISCH output goes
high, and the I_FLT digital output becomes asserted.
The use of an external C
RETRY
capacitor sets the auto-
retry time, t
RETRY
, according to the internal V
RETRYH
threshold voltage and the CRETRY pin charging
current, I
RETRYUP
[t
RETRY
= C
RETRY
* (V
RETRYH
/I
RETRYUP
)].
Prior to the tripping of the OC circuit breaker, a 3mA
current sink is enabled holding the CRETRY pin
voltage at 0V. When the OC circuit breaker has been
tripped, the 3mA current sink is disabled and a 3礎
current source is enabled to charge the external
C
RETRY
capacitor. When C
RETRY
has charged above
V
RETRYH
, the circuit breaker is reset such that the
I_FLT digital output is de-asserted. Additionally, the
3礎 current source is disabled and the 3mA current
sink is enabled to discharge the CRETRY pin voltage
back to 0V. When C
RETRY
has discharged below
V
RETRYL
, the GATE drive circuit is re-enabled and the
DISCH output returns low. For the case of a persistent
overcurrent load, the controller will continuously cycle
between starting up into an OC condition that trips the
circuit breaker and the auto-retry time before the
circuit breaker is reset.
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