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参数资料
| 型号： | MIP7365-450F24M |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 450 MHz, MICROPROCESSOR, CQFP208 |
| 封装： | 1.20 X 1.20 MM, CERAMIC, QFP-208 |
| 文件页数： | 12/16页 |
| 文件大小： | 285K |
| 代理商： | MIP7365-450F24M |
5
SCD7365 Rev B 1/11/07
Aeroflex Plainview
Clock/Control Interface
PIN NAME
TYPE
DESCRIPTION
Master Clock
Input
System clock
Master clock input used as the system interface reference clock. All output timings are relative
to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the
factor selected during boot initialization.
Power Supply
PIN NAME
TYPE
DESCRIPTION
VccInt
Input
Power supply for core.
VccIO
Input
Power supply for I/O.
VccP
Input
Vcc for PLL
Quiet VccInt for the internal phase locked loop. Must be connected to VccInt through a filter
circuit.
VccJ
Input
Power supply used for JTAG.
Vss
Input
Ground Return.
VssP
Input
Vss for PLL
Quiet Vss for the internal phase locked loop. Must be connected to Vss through a filter circuit.
Interrupt Interface
PIN NAME
TYPE
DESCRIPTION
INT[9:0]*
Input
Interrupt
Ten general processor interrupts, bit-wise ORed with bits 9:0 of the interrupt register.
NMI*
Input
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 15 of the interrupt register (bit 6 in R5000
compatibility mode).
JTAG Interface
PIN NAME
TYPE
DESCRIPTION
JTDI
Input
JTAG data in
JTCK
Input
JTAG clock input
JTDO
Output
JTAG data out
JTMS
Input
JTAG command
JTRST*
Input
JTAG reset.
Notes:
1. The JTRST* input was added to the RM70xxC and RM79xx CPUs to directly control the reset to the JTAG state machine. JTAG boundary
scan test equipment must be able to drive JTRST* high to allow JTAG boundary scan operation.
2. The JTRST* input must be connected to GND (Vss) through a 220
Ω to 1 KΩ pull-down resistor to force the JTAG state machine into the
reset state to allow normal operation (JTAG boundary scan mode disabled).
3. The JTAG interface electrical characteristics are dependent on the VccJ level chosen (2.5 V or 3.3 V).
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