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| 型号： | MJ80C52XXX-12 |
| 厂商： | TEMIC SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, QCC44 |
| 封装： | LCC-44 |
| 文件页数： | 39/108页 |
| 文件大小： | 3682K |
| 代理商： | MJ80C52XXX-12 |
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36
8069R–AVR–06/2013
XMEGA A4
Not recommended for new designs -
Use XMEGA A4U series
20. TWI - Two-Wire Interface
20.1
Features
Two Identical TWI peripherals
Simple yet Powerful and Flexible Communication Interface
Both Master and Slave Operation Supported
Device can Operate as Transmitter or Receiver
7-bit Address Space Allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Up to 400 kHz Data Transfer Speed
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition Causes Wake-up when in Sleep Mode
I2C and System Management Bus (SMBus) compatible
20.2
Overview
The Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock
(SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 indi-
vidually addressable devices. Since it is a multi-master bus, one or more devices capable of
taking control of the bus can be connected.
The only external hardware needed to implement the bus is a single pull-up resistor for each of
the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE,
respectively.
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