参数资料
型号: MK2049-11SI
元件分类: 时钟产生/分配
英文描述: 56 MHz, OTHER CLOCK GENERATOR, PDSO20
封装: 0.300 INCH, SOIC-20
文件页数: 11/13页
文件大小: 166K
代理商: MK2049-11SI
Communications Clock PLL
MDS 2049-11 C
7
Revision 021402
Integrated Circuit Systems, Inc. q 525 Race Street San Jose, CA 95126 q tel (408) 295-9800 q
www.icst.com
MK2049-11
capacitor should be a tantalum type, 1
F minimum.
The other capacitors should be ceramic type.
The power supply traces to the individual VDD pins
should fan out at the common supply filter to reduce
interaction between the device circuit blocks.
The decoupling capacitors at the VDD pins should be
ceramic type and should be as close to the VDD pin
as possible. There should be no via’s between the
decoupling capacitor and the supply pin.
Recommended Power Supply Connection
Series Termination Resistor
Output clock PCB traces over 1 inch should use series
termination to maintain clock signal integrity and to
reduce EMI. To series terminate a 50
trace, which is a
commonly used PCB trace impedance, place a 33
resistor in series with the clock line as close to the clock
output pin as possible. The nominal impedance of the
clock output is 20
.
Quartz Crystal
The MK2049-11 operates by phase-locking the VCXO
circuit to the input signal at the ICLK input. The VCXO
consists of the external crystal and the integrated
VCXO oscillator circuit. To achieve the best
performance and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section shown must be followed.
The frequency of oscillation of a quartz crystal is
determined by its cut and by the load capacitors
connected to it. The MK2049-11 incorporates variable
load capacitors on-chip which “pull” or change the
frequency of the crystal. The crystals specified for use
with the MK2049-11 are designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14pF. To achieve this, the layout should
use short traces between the MK2049-11 and the
crystal.
Recommended Crystal Parameters:
Operating Temperature Range
Commercial Applications
0 to 70
°C
Industrial Applications
-40 to 85
°C
Initial Accuracy at 25
°C
±20 ppm
Temperature Stability
±30 ppm
Aging
±20 ppm
Load Capacitance
14 pF
Shunt Capacitance, C0
7 pF Max
C0/C1 Ratio
250 Max
Equivalent Series Resistance
35
Max
Note: Crystals used in production should be screened
for 3rd overtone modes and spurs over the range of (3x
crystal frequency) +/- 100ppm, when measured at the
nominal parallel resonant frequency. Failure to do so
may cause locking problems in a small percentage of
production systems at certain input frequencies.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small
capacitors from X1 and X2 to ground, shown as CL in
the Block Diagram on page 1. These capacitors are
optional and may be later used to center the total load
capacitor adjustment range imposed on the crystal.
The load adjustment range includes stray PCB
capacitance that varies with board layout. Because the
typical telecom reference frequency is accurate to less
Connection Via to
5V Power Plane
Ferrite
Chip
0.
1
F
BULK
1
n
F
VDD
Pin
0.0
1
F
VDD
Pin
0.
01
F
VDD
Pin
0.
0
1
F
VDD
Pin
0.
01
F
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