参数资料
型号: MK2049-11SI
元件分类: 时钟产生/分配
英文描述: 56 MHz, OTHER CLOCK GENERATOR, PDSO20
封装: 0.300 INCH, SOIC-20
文件页数: 7/13页
文件大小: 166K
代理商: MK2049-11SI
Communications Clock PLL
MDS 2049-11 C
3
Revision 021402
Integrated Circuit Systems, Inc. q 525 Race Street San Jose, CA 95126 q tel (408) 295-9800 q
www.icst.com
MK2049-11
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
NC
-
No internal connection, may be tied high or low, or left floating.
2
X2
-
Crystal Output. Connect this pin to the external reference crystal.
3
X1
-
Crystal Input. Connect this pin to the external reference crystal.
4
VDD
Power
Power Supply. Connect to +5V.
5
VDD
Power
Power Supply. Connect to +5V.
6
VDD
Power
Power Supply. Connect to +5V.
7
GND
Power
Ground.
8
CLK2
Output
Clock output, frequency determined by status of FS3:1 per table on
page 2.
9
CLK1
Output
Clock output, frequency determined by status of FS3:1 per table on
page 2.
10
8k
Output
8.000kHz Clock Output, applicable modes only, refer to table on page 2.
11
FS2
Input
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
12
FS3
Input
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
13
ICLK
Input
Input Clock Connection.
14
GND
Power
Ground.
15
VDD
Power
Power Supply. Connect to +5V.
16
CAP1
-
Loop Filter Connection. Refer to Block Diagram on page 1.
17
GND
Power
Ground.
18
CAP2
-
Loop Filter Connection. Refer to Block Diagram on page 1.
19
FS1
Input
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
20
NC
-
No internal connection, may be tied high or low, or left floating.
相关PDF资料
PDF描述
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