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ML66525 Family User’s Manual
Chapter 17 USB Control Function
17 - 15
17.3.9
Internal DMA (Direct Memory Access)
It is possible to carry out 8-bit wide internal DMA transfer for the bulk transfer of EP1, EP2, EP4,
and EP5, and for the isochronous transfer of EP4 and EP5.
It is possible to carry out internal DMA transfers over two channels, Channel 0 and Channel 1.
Both demand transfer and single transfer are supported. The settings of the internal DMA
transfer mode and parameters are done using the DMA control register and the DMA interval
register described later in this manual.
In the demand transfer mode, the DREQ signal is asserted when the reading or writing of a data
packet becomes possible. The DREQ signal is de-asserted when the transfer of all the data of the
receive packets is completed by the internal DMA controller. Therefore, other devices cannot
access the local bus during DMA transfer.
On the other hand, in the single transfer mode, the DREQ signal is de-asserted at the end of
transfer of the number of bytes of one transfer, and the other devices can access the local bus
during this period.
17.3.10 Power-down
When the USB controller detects a suspended state on the USB bus, it automatically stops the
PLL and the USB control function enters the power-down state. At this time, if OSCS (bit 3 of
SBYCON) is “1” and the CPU is either in the STOP mode or operating under the subclock, the
OSC oscillation circuit stops (see Chapter 3). When the resume signal is detected on the USB
bus, the OSC oscillation circuit is activated even if the CPU is in the STOP mode or operating
under the subclock, and the PLL circuit is enabled at the same time, so that the power-down state
of the USB control function is released.
Writing a “1” and a “0” to the OSCTEST register bit 2 and bit 1 respectively forces the USB
control function to enter a power-down state. Power saving can be made real when the USB bus
is unconnected (USB not used).