ML66525 Family User’s Manual
Chapter 5
Port Functions
5 - 35
Table 5-14 lists the data that is read, depending on the settings of P10IO and P10SF, when
executing an instruction to read P10.
At reset (due to a RESn input, BRK instruction execution, watchdog timer overflow, or opcode
trap), P10 will become a high impedance input port (P10IO = 00H, P10SF = 00H) and the
contents of P10 will be 00H.
Table 5-14
P10 Read Data
P10IO
P10SF
Read data
0
*
P10_0/SIOCK3 pin state
1
0
Value of bit 0 of P10 (port data register)
P10_0
1
SIOCK3 output data
0
*
P10_1/SIOI3 pin state
1
0
Value of bit 1 of P10 (port data register)
P10_1
1
“0”
0
*
P10_2 pin state
1
0
Value of bit 2 of P10 (port data register)
P10_2
1
SIOO3 output data
0
*
P10_4 pin state
1
0
Value of bit 4 of P10 (port data register)
P10_4
1
SIOO4 output data
0
*
P10_5 pin state
1
0
Value of bit 5 of P10 (port data register)
P10_5
1
“0”
“*” indicates “0” or “1”
[Note]
If arithmetic, SB, RB, XORB or other read-modify-write instructions are executed
for P10, depending on the settings of P10IO and P10SF, values will be read as
listed in Table 5-14.
The modified values will be written to P10 (port 10 data
register).
However, regarding the P10_3/SIOCK4 pin, the output setting of the pin also requires the
setting using bit 5 (SCK4IO) of the internal control register (P5IO).
In other words, when
using P10_3 as an output (primary or secondary function), it is required to set SCK4IO to “1”
in addition to setting P10IO3 to “1”.
Further, the polarity of the P10_3/SIOCK4 pin can be selected for both input and output using
bit 4 (SCK4INV) of the internal control register (P5IO).
The polarity of the P10_3/SIOCK4
pin will be positive when SCK4INV is set to “0”, and negative when SCK4INV is set to “1”.
When a read instruction is executed for P10_3, the content of the data that is read out is given
in Table 5-15 depending on the settings of P10IO3, P10SF3 or SCK4IO, and SCK4INV.
The
shaded portions are the modes that are not normally set.