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ML66525 Family User’s Manual
Chapter 19
Internal DMA Control Function
19 - 7
(5)
Interrupt status register (INTSTAT)
This register is used for the CPU to read the status of the DMA controller.
The bits 0 and 1 indicate whether the corresponding channel has reached the TC (terminal
count) condition or not, and are set when the terminal count condition has been reached (When
there is a transition of the word count value from 0001H to 0000H).
The bits 2 and 3 indicate that a short packet has been received in the EP of the corresponding
channel.
These bits are set when all the data of the short packet has been transferred to the
buffer RAM.
The bit 7 is set to “1” when the mask registers of both channels have been set to “1” and also
the DMA transfer has been stopped.
In this condition, the access from the CPU to the
registers of the USB controller becomes enabled.
In the case of bits 0 to 3, the corresponding interrupt request can be cleared by writing 1s to
these bits.
The interrupt request cannot be cleared by writing 0s to these bits.
In order to clear the interrupt request of bit 7, bit 7 of the interrupt enable register (INTENBL)
must be reset to a “0”.
INTSTAT can be read from and written to by the program. However, write operations are
invalid for bits 4 to 6. If read, a value of “0” will always be obtained for bits 4 to 6.
When reset (RESn signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), INTSTAT becomes 00H.
Figure 19-9 shows the INTSTAT configuration.
7
6
5
4
3
2
1
0
INTSTAT
-
At reset
0
No request from channel 0 TC interrupt
1
Request from channel 0 TC interrupt
0
No request from channel 1 TC interrupt
1
Request from channel 1 TC interrupt
0
No request from channel 0 short packet
interrupt
1
Request from channel 0 short packet
interrupt
0
No request from channel 1 short packet
interrupt
1
Request from channel 1 short packet
interrupt
0
No request from DMA transfer stop
interrupt
1
Request from DMA transfer stop
interrupt
Figure 19-9
INTSTAT Configuration
Address : 1A90[H]
R/W access : R/W