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参数资料
| 型号： | ML67Q4061LA |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | RISC MICROCONTROLLER, PBGA84 |
| 封装： | 9 X 9 MM, 0.80 MM PITCH, PLASTIC, LFBGA-84 |
| 文件页数： | 20/26页 |
| 文件大小： | 364K |
| 代理商： | ML67Q4061LA |
ML67Q4050/Q4060 Series
FUNCTIONAL DESCRIPTION
June 2006, Rev 1.2
Oki Semiconductor 3
FUNCTIONAL DESCRIPTION
CPU
- 32-bit RISC CPU (ARM7TDMI)
- Little endian byte order
- Maximum operating frequency: 33.33 MHz
- Instruction set: Free switching between a highly efficient 32-bit instruc-
tion set, and a 16-bit subset offering higher object code density
- General-purpose registers: 31 32-bit registers
- Barrel shifter: Simultaneous ALU and barrel shift operations in the
same instruction
- Multiplier (32-bit x 8-bit)
- JTAG interface for debugging
Built-in Memory
- SRAM: 16KBytes (4K x 32 bits), 1-cycle access
- Built-in Flash ROM: 128KBytes (ML67Q4051, ML67Q4061) or
64KBytes (ML67Q4050, ML67Q4060), 1-cycle access, connected to
the processor bus Flash ROM programming cycle count: 100 (max.)
- Boot ROM: 8KBytes
External Memory Controller (only for ML67Q4050/51)
- Programmable access timing setting for each space
- ROM (Flash) access function
- Supports 1 bank x 8KBytes ROM space.
- Supports 16-bit and 32-bit devices
- Supports flash memories
- Supports page accessing
- SRAM access function
- Supports 1 bank x 8MBytes SRAM space.
- Supports 16-bit and 32-bit devices.
- Supports asynchronous SRAM.
- External I/O access function
- Supports 2-bank I/O space.
- Supports 8-bit, 16-bit, and 32-bit devices.
- Supports asynchronous wait from external devices.
- Allows address setup in units of single cycles, RE/WE pulse, and
data-off timing setting.
Interrupt Controller
- One fast interrupt (FIQ) source (external)
- 31 interrupt (IRQ) sources (40 interrupt sources for ML67Q4050/51)
- Independent masking for each FIQ and IRQ source
- Independent interrupt priority level settings for each IRQ source
- Priority control blocking IRQ requests with priority levels at or below
those for interrupt requests currently being processed
System Timers
- One 16-bit system timer
Flexible Timers
- Six 16-bit flexible timers
- Auto Reload Timer (ART) / Compare Out (CMO) / Pulse Width Mod-
ulation (PWM) / Capture (CAP)
Watchdog Timer
- One 16-bit timer
- Choice of interrupt or reset on overflow
- Maximum period: 8.94 sec. (at Peripheral clock = 30 MHz)
- Change watch dog period while running counting
- Setting of period asserting reset signal (RSTOUT_N)
SIO
- Full duplex asynchronous operation
- Built-in baud-rate generator
DMA Controller
- Two channels
- Selectable DMA request source, source peripheral: I2S, I2C, UART, SPI
(External DMA request is available only for ML67Q4050/51)
- Choice of fixed or round robin mode for channel priority order
- Choice of cycle-steal or burst mode for requesting bus access
- Choice of software or external DMA transfer requests
- Maximum transfer count: 65,535
- Data transfer sizes: 8-, 16-, and 32-bit
GPIO
- Three 20-mA sink pins
- Individual settings for pin I/O direction
- Individual settings for pin interrupt requests
- One 8-bit port, two 7-bit ports, three 6-bit ports
- For ML67Q4050/51 series:
- Eight 8-bit ports
- Three 7-bit ports
- Three 6-bit ports
- One 5-bit port
- For ML67Q4060/61 series:
- One 8-bit ports
- Two 7-bit ports
- Three 6-bit ports
Analog-to-Digital Converter
- Four channels of 10-bit resolution, each using consecutive comparison
- Sample and hold function
- Choice of scan or select operation
- Conversion time: 20
μs (MAX 50k-sample/s)
- DNL (MAX) =
± 6.0 LSB
- INL (MAX) =
± 6.0 LSB
- Zero Scale Error (MAX) =
± 8.0 LSB
- Full Scale Error (MAX) =
± 8.0 LSB
UART
- Two 16550A-compatible asynchronous communications
- Independent 16-byte FIFOs for transmit and receive operations
- Full duplex operation
- Built-in baud-rate generator
- Supports DMA transfers
I2C
- Controller in conformity of I2C bus specification ver2.1
- Multi Master support
- Supports fast mode (400 kbps), standard mode (100 kbps)
- Supports 7-bit, 10-bit address
- Supports DMA transfers
I2S Transmitter/Receiver
- Conforms to I2S (the Inter-IC Sound) specification for DAC/ADC I/F
- Three-line communication, bit clock (SCK), word clock (WS), serial
data (SD)
- Supports Master/Slave
- Word Clock: 32fs / 64fs
- Channel data length: 16/18/20/24-bit (16-bit CPU I/F)
- Support 1-bit delay, reverse L-Ch and R-Ch
- Supports DMA
- One 256 x 16-bit FIFO shared Transmitter/Receiver
- Master clock output
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| ML67Q5002 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:32-bit ARM-Based General-Purpose Microcontroller |
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