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参数资料
| 型号： | ML67Q4061LA |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | RISC MICROCONTROLLER, PBGA84 |
| 封装： | 9 X 9 MM, 0.80 MM PITCH, PLASTIC, LFBGA-84 |
| 文件页数： | 26/26页 |
| 文件大小： | 364K |
| 代理商： | ML67Q4061LA |
ML67Q4050/Q4060 Series
Pin Configuration
June 2006, Rev 1.2
Oki Semiconductor 9
Pin Descriptions
The pins of the ML67Q4050/Q4060 Series devices have multiple uses
which are shown in detail in “I/O Functions Share Pin Locations” on
page 12. The selection of function used is defined in Chapter 5 the
“ML67Q4050/Q4060 Series User’s Manual”. The following table
provides the description and function of the pins when they are
selected/enabled. The Functions are defined as 1st (primary) / 2nd
(secondary) / 3rd (tertiary). The “Initial Function at Reset” overrides
other functions and is used until the device is configured.
Pin Descriptions
Symbol
I/O
Description
Function Level
1st
2nd
3rd
System
SYSCLK_P
I
System Clock
SYSCLK_N
O
RTCCLK_P
I
32.768 kHz RTC Clock
RTCCLK_N
O
RESET_N
I
System Reset input (Active-Low)
RSTOUT_N
O
Reset output (Active-Low) – shares pin with PA6
Mode
TEST1
I
System Test 1
TEST2
I
System Test 2
BOOT0
I
Power-up default, selects boot device – shares pin with PE3
Initial Function
at Reset
BOOT1
I
Power-up default, selects boot device – shares pin with PO4
BOOTCLK
I
Power-up default, Boot Clock – shares pin with PD5
Debug and Boundary Scan Support
JTAGE
I
Power-up default, JTAG Test Enable – shares pin with PA5
Initial Function
at Reset
TCK
I
Power-up default, JTAG Clock – shares pin with PA0
TMS
I
Power-up default, JTAG Mode Select – shares pin with PA1
NTRST
I
Power-up default, Resets JTAG function (Active Low) – shares pin with PA4
TDI
I
Power-up default, JTAG Data Input – shares pin with PA2
TDO
O
Power-up default, JTAG Data Output – shares pin with PA3
BS
I
Power-up default, boundary scan select – shares pin with PD4
External Memory Control Signal (ML67Q4050/4051 Only)
XA [22:0]
O
23-bit Address bus for external devices
XD [31:0]
I/O
32-bit Data bus for external devices
EXBUSE
I
Power-up default, memory bus enable – shares pin with PO2
Initial Function
at Reset
EXIROME
I
Power-up default, memory access enable – shares pin with PO3
OE_N
O
Memory access read enable (Active-Low) – shares pin with PO0
WR_N
O
Memory access write enable (Active-Low) – shares pin with PO1
ROMCS_N
O
ROM chip select (Active-Low) – shares pin with PN0
RAMCS_N
O
RAM chip select (Active-Low) – shares pin with PN1
BS0/1/2/3_N
O
Four memory byte selects (Active-Low) – shares pin with PN4/5/6/7
IOCS0_N
O
I/O bank 1, chip select 0 (Active-Low) – shares pin with PN2
IOCS1_N
O
I/O bank 1, chip select 1 (Active-Low) – shares pin with PN3
External DMA Control (ML67Q4050/51 Only)
DMAREQ
I
DMA request – used to request a DMA transfer – shares pin with PI5
DMACLR
O
DMA Clear – signals completion of DMA transfers – shares pin with PI6
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