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参数资料
| 型号： | ML67Q4061LA |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | RISC MICROCONTROLLER, PBGA84 |
| 封装： | 9 X 9 MM, 0.80 MM PITCH, PLASTIC, LFBGA-84 |
| 文件页数： | 22/26页 |
| 文件大小： | 364K |
| 代理商： | ML67Q4061LA |
ML67Q4050/Q4060 Series
Pin Configuration
June 2006, Rev 1.2
Oki Semiconductor 5
Pin Configuration
Figure 1. 144-Pin Plastic LQFP
Notes:
1. For pins that have multiple functions, the signals are noted by their
Initial / primary / secondary / tertiary functions. See “Pin Descriptions”
Table for details.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
BS1_N/PN5
GND
PB3/RX1/EXINT1
BS3_NPN7
XA1/PG0
XA2/PG1
PB4/SCL/TXD
XA3/PG2
XA4/PG3
XA5/PG4
XA6/PG5
PB5/SDA/RXD
VDD_IO
PE0
GND
PE1
GND
PE2
VDD_IO
PD0/AIN0/EXINT2
PD1/AIN1/EXINT3
PD2/AIN2
PD3/AIN3
XA7/PG6
XA8/PH0
XA10/PH2
TEST1
XA11/PH3
XA12/PH4
XA13/PH5
TEST2
XA14/PH6
GND
XA15/PH7
XA9/PH1
XA1
6/P
I0
XA1
7/P
I1
VDD_
CORE
XA1
8/P
I2
VD
D
_I
O
XA
[19
[/P
I3
GND_
PLL
GND_
PLL
XA2
0/P
I4
VDD_
PLL
VDD_
PLL
XA
21
/PI5
/DM
AREQ
RTC
C
LK_
N
RTCCL
K_
P
GN
D
GN
D
SY
SCLK
_P
SYSCL
K_N
XA
22
/PI
6/DM
ACLR
TCK/P
A0
TMS/P
A1
TDI/P
A2
TDO/P
A3
XA
0/P
I7
VD
D
_I
O
XD31
/PM
7
XD30
/PM
6
XD29
/PM
5
JTAG
E/P
A5
XD28
/PM
4
XD27
PM
3
XD26
/PM
2
VDD_
CORE
XD25
/PM
1
NTRST/P
A4
XD
24
25
/PM
0
XD8’/PK0
GND
BOOTCLK/PD5
XD9/PK1
XD10/PK2
XD11/PK3
PC0/MISO0DSR0
XD12/PK4
XD13/PK5
VDD_IO
XD14/PK6
XD15/PK7
PC1/MOIS0/DTR0
PC2/SCK0/RI0
PC3/SSN0/DCD0
PC4/MISO1/DSR1
PC5/MOSI1/DTR1
XD16/PL0
RESET_N
GND
PC6/SCK1/RI1
PC7/SSN1/DCD1
BS/PD4
XD17/PL1
VDD_IO
XD18/PL2
XD19/PL3
PE5/WS
XD20/PL4
GND
RSTOUT_N/PA6/MCLK
XD21/PL5
XD22/PL6
PE6/SCK
GND
XD23/PL7
OE_
N
/PO0
ROMC
S_
N/P
N
0
VDD_
CORE
RAMCS_
N/P
N
1
IOCS0_
N/P
N
2
IOCS1_
N/P
N
3
BOO
T1/PO
4
VDD_
IO
EXI
ROME
/PO
3
GND
WR
_N
/PO1
BS0
_N/P
N4
PB0
/TX0
PB1
/RX0
PB2
/TX1
/EFIQ
_N
BOO
T0/PE
3/M
C
LK
PE4
/SS
D
PF0/
TIMER0/CTS0
PF1/
TIMER1/RTS0
PF2/
TIMER2/CTS1
PF5/
TIM
ER5/E
XINT5
VDD_
IO
XD0/
PJ0
XD1/
PJ1
EXB
USE/P
O
2
GND
NC
XD2/
PJ2
XD3/
PJ3
PF3/
TIMER3/RTS1
2
PF4/
TIM
ER4/E
XINT4
XD4/
PJ4
XD5/
PJ5
VDD_
CORE
XD6/
PJ6
XD7/
PJ]7
\
ML67Q4050/51
144-Pin LQFP
(TOP VIEW)
BS2_N/PN6
Index Mark
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