参数资料
型号: MM908E622ACDWB/R2
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54
封装: 17.90 X 7.50 MM, 0.65 MM PITCH, PLASTIC, SOIC-54
文件页数: 25/66页
文件大小: 1277K
代理商: MM908E622ACDWB/R2
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
908E622
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
POR— Power On Reset Bit
This read/write bit is set after power on. The bit is cleared
by writing a logic “1” to this location.
1 = Reset due to power on
0 = no power on reset
PINR— Reset Forced from External Reset Pin Bit
This read/write bit is set after a reset was forced on the
external reset RST_A pin. The bit is cleared by writing a logic
“1” to this location.
1 = reset source is external reset pin
0 = no external reset
WDR— Watch Dog Reset Bit
This read/write flag is set due to watchdog timeout or a
wrong watchdog timer reset. Clear WDR by writing a logic “1”
to WDR.
1 = reset source is watchdog
0 = no watchdog reset
HTR— High Temperature Reset Bit
This read/write bit is set if the chip temperature exceeds a
certain value. The bit is cleared by writing a logic “1” to this
location.
1 = reset due to high temperature condition
0 = no high temperature reset
LVR— Low Voltage Reset Bit
This read/write bit is set if the external VDD voltage coming
from the main voltage regulator falls below a certain value. Bit
is cleared by writing a logic “1” to this location.
1 = reset due to low voltage condition
0 = no low voltage reset
LINWF— LIN Wake-up Flag
This read/write bit is set if a bus activity was the case of an
wake-up. Bit is cleared by writing a logic “1” to this location.
1 = Wake-up due to bus activity
0 = no wake-up due to bus activity
L0WF— L0 Wake-up Flag
This read/write bit is set if a event on the L0 pin caused an
wake-up. Bit is cleared by writing a logic “1” to this location.
1 = Wake-up due to L0 pin
0 = no Wake-up due to L0 pin
ANALOG DIE INPUTS/OUTPUTS
LIN PHYSICAL LAYER
The LIN bus pin provides a physical layer for single-wire
communication in automotive applications. The LIN physical
layer is designed to meet the LIN physical layer specification.
The LIN driver is a low side MOSFET with internal current
limitation and thermal shutdown. An internal pull-up resistor
with a serial diode structure is integrated, so no external pull-
up components are required for the application in a slave
mode. The fall time from dominant to recessive, and the rise
time from recessive to dominant is controlled. The symmetry
between both slew rate controls is guaranteed.
The slew rate can be selected for optimized operation at
10 and 20kBit/s, as well as high baud rates for test and
programming. The slew rate can be adapted with 2 bits
SRS[1:0] in the System Control Register. The initial slew rate
is optimized for 20kBit/s.
The LIN pin offers high susceptibility immunity level from
external disturbance, guaranteeing communication during
external disturbance.
The LIN transmitter circuitry is enabled by setting the
PSON bit in the System Control Register (SYSCTL).
If the transmitter works in the current limitation region, the
LINCL bit in the System Status Register (SYSSTAT) is set
and the LIN transceiver is disabled after a certain time.
For improved performance and safe behavior when the
LIN bus shorts to Ground, or LIN bus leakage during low
power mode, the internal pull-up resistor on the LIN pin is
disconnected from VSUP and a small current source keeps
the LIN bus at recessive level. In case of a LIN bus short to
GND, this feature will reduce the current consumption in
STOP and SLEEP modes.
Register Name and Address: RSR - $0D
Bit7
6
5
4
3
2
1
Bit0
Read
POR
PINR
WDR
HTR
LVR
0
LINWF LOWF
Write
POR
1
0
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