参数资料
型号: MM908E622ACDWB
厂商: Freescale Semiconductor
文件页数: 43/63页
文件大小: 0K
描述: IC QUAD HALF BRDG TRPL SW 54SOIC
标准包装: 26
应用: 自动镜像控制
核心处理器: HC08
程序存储器类型: 闪存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
输入/输出数: 12
电源电压: 9 V ~ 16 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 54-BSSOP(0.295",7.50mm 宽)裸露焊盘
包装: 管件
供应商设备封装: 54-SOICW-EP
Analog Integrated Circuit Device Data
48
Freescale Semiconductor
908E622
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Factory TRIMMING AND CALIBRATION
To enhance the ease-of-use of the 908E622, various
parameters (e.g. ICG trim value) are stored in the flash
memory of the device. The following flash memory locations
are reserved for this purpose and might have a value different
from the “empty” ($FF) state:
$FD80:$FDDF Trim and Calibration Values
$FFFE:$FFFF Reset Vector
In the event the application uses these parameters, one
has to take care not to erase or override these values. If these
parameters are not used, these flash locations can be erased
and otherwise used.
Trim Values
The usage of the trim values located in the flash memory
is explained by the following.
Internal Clock Generator (ICG) Trim Value
The internal clock generator (ICG) module is used to
create a stable clock source for the microcontroller, without
using any external components. The untrimmed frequency of
the low frequency base clock (IBASE) will vary as much as
±25 percent due to process, temperature, and voltage
dependencies. To compensate these dependencies, a ICG
trim value is located at address $FDC2. After trimming, the
ICG is in a range of typ. ±2% (±3% max.) at nominal
conditions (filtered (100 nF), and stabilized (4.7
μF)
VDD = 5.0 V, TAMBIENT~25°C), and will vary over
temperature and voltage (VDD), as indicated in the
68HC908EY16 datasheet.
To trim the ICG, this value has to be copied to the ICG Trim
Register ICGTR at address $38 of the MCU.
Important The value has to copied after every reset.
Watchdog Period Range Value (AWD Trim)
The window watchdog supervises device recovery (e.g.
from code runaways).
The application software has to clear the watchdog within
the open window. Due to the high variation of the watchdog
period, and therefore the reduced width of the watchdog
window, a value is stored at address $FDCF. This value
classifies the watchdog period into 3 ranges (Range 0, 1, 2).
It allows the application software to select one of three time
intervals to clear the watchdog based on the stored value.
The classification is done in a way that the application
software can have up to ±19% variation of the of optimal clear
interval, e.g. caused by ICG variation.
Effective Open Window
Having a variation in the watchdog period in conjunction
with a 50% open window, results in an effective open window,
which can be calculated by:
latest window open time: t_open = t_wd max / 2
earliest window closed time: t_closed = t_wd min
$08
A0 and Multiplexer
Control (A0MUCTL)
R
CSON
CSSEL1
CSSEL0
CSA
SS3
SS2
SS1
SS0
W
$09
Interrupt Mask
(IMR)
R
L0IE
H0IE
LINIE
HTRD
HTIE
LVIE
HVIE
PSFIE
W
$0A
Interrupt Flag
(IFR)
R
L0IF
H0IF
LINIF
0
HTIF
LVIF
HVIF
PSFIF
W
$0B
Watchdog Control
(WDCTL)
R
WDRE
WDP1
WDP0
0
W
WDRST
$0C
System Status
(SYSSTAT)
R
LINCL
HTIF
VF
H0F
HVDDF
HSF
HBF
ECF
W
$0D
Reset Status
(RSR)
R
POR
PINR
WDR
HTR
LVR
0
LINWF
L0WF
W
$0E
System Test
(SYSTEST)
R
reserved
W
$0F
System Trim 1
(SYSTRIM1)
R
HVDDT1
HVDDT0
reserved
itrim3
itrim2
itrim1
itrim0
W
$10
System Trim 2
(SYSTRIM2)
R0
0
W
CRHBHC1 CRHBHC0
CRHB5
CRHB4
CRHB3
CRHB2
CRHB1
CRHB0
$11
System Trim 3
(SYSTRIM3)
R0
0
W
CRHBHC3 CRHBHC2
CRHS5
CRHS4
CRHS3
CRHS2
CRHS1
CRHS0
Table 13. SPI Register Overview
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