Chapter 2
Basic CPU
II - 2
Overview
2-1
Overview
The MN101C series has a flexible optimized hardware configuration as an embedded microcomputer
and a simple, efficient instruction set for both economy and speed. Specific features are as follows:
Table 2-1-1
Basic Specifications
1. Minimized code sizes with instruction lengths based on 4-bit increments
The series keeps code sizes down by adopting a basic instruction length of one byte and variable
word lengths based on 4-bit increments. As a result, the series minimizes code sizes in spite of its
simple instruction set limiting data transfers to and from memory to load/store operations.
2. Minimum instruction execution time of one cycle in this LSI is 100 ns .
3. Minimized register set that simplifies the architecture and supports C language
The instruction set has been determined, depending on the size and capacity of hardware, after
an analysis of embedded application programing code and creation code by C language compiler.
Therefore, the set is simple instruction using the minimal register set required for C language
compiler. [
MN101C LSI User's Manual" (Architecture Instructions) ]
Structure
Load / store architecture
Six registers
Data : 8-bit x 4
Address : 16-bit x 2
Other
PC : 19-bit
PSW : 8-bit
SP : 16-bit
Instructions
Number of instructions
37
Addressing modes
9
Instruction length
Basic portion : 1 byte (min.)
Extended portion : 0.5-byte x n
(0
≤n≤9)
Basic
performance
Internal operating frequency (max)
10 MHz
Instruction execution
Min. 1 cycle
Inter-register operation
Min. 2 cycles
Load / store
Min. 2 cycles
Conditional branch
2 to 3 cycles
Pipeline
3-stage (instruction fetch, decode, execution)
Address space
256 KB (max. 64 KB for data)
Instruction / data common space
External bus
Address
18-bit (max.)
Data
8-bit
Minimum bus cycle
1 clock (100 ns)
Interrupt
Vector interrupt
3 interrupt levels
Low-power
dissipation mode
STOP mode
HALT mode