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参数资料
型号： MOBILE AMD-K6
厂商： Advanced Micro Devices, Inc.
英文描述： 32 Bit Microprocessor With 64-K Byte Level-one Cache and Advanced RISC86 Superscalar Microarchitecture(32位微处理器带64K字节高速缓存和高级的RISC86超标量微体系结构)
中文描述： 32位微处理器的64亩字节的一级缓存和高级RISC86超标微架构（32位微处理器带64K的字节高速缓存和高级的RISC86超标量微体系结构）
文件页数： 18/108页
文件大小： 2267K
代理商： MOBILE AMD-K6
8
Internal Architecture
Chapter 2
Mobile AMD-K6
Processor Data Sheet
21049H/0—September 1998
Preliminary Information
used for predicting conditional branches. Because the branch
history table does not store predicted target addresses, special
address ALUs calculate target addresses on-the-fly during
instruction decode. The branch target cache augments
predicted branch performance by avoiding a one clock
cache-fetch penalty. This specialized target cache does this by
supplying the first 16 bytes of target instructions to the
decoders when branches are predicted. The return address
stack is a unique device specifically designed for optimizing
CALL and RETURN pairs. In summary, the mobile AMD-K6
uses dynamic branch logic to minimize delays due to the branch
instructions that are common in x86 software.
Mobile AMD-K6
Processor Block Diagram.
As shown in Figure 1 on
page 9, the high-performance, out-of-order execution engine of
the mobile AMD-K6 processor is mated to a split level-one
64-Kbyte writeback cache with 32 Kbytes of instruction cache
and 32 Kbytes of data cache. The instruction cache feeds the
decoders and, in turn, the decoders feed the scheduler. The ICU
issues and retires RISC86 operations contained in the
scheduler. The system bus interface is an industry-standard
64-bit Pentium processor demultiplexed bus.
The mobile AMD-K6 processor combines the latest in
processor microarchitecture to provide the highest x86
performance for today’s personal computers. The mobile
AMD-K6 offers true sixth-generation performance and full x86
binary software compatibility.
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