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参数资料
| 型号： | MPC5125YVN200 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 200 MHz, MICROCONTROLLER, PBGA324 |
| 封装： | 23 X 23 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-034AJJ-1, TEPBGA-324 |
| 文件页数： | 65/92页 |
| 文件大小： | 640K |
| 代理商： | MPC5125YVN200 |
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MPC5125 Microcontroller Data Sheet, Rev. 3
Electrical and Thermal Characteristics
Freescale Semiconductor
68
4.3.11
DIU
The DIU is a display controller designed to manage the TFT LCD display.
4.3.11.1
Interface to TFT LCD Panels, Functional Description
Figure 33 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with
positive polarity. The sequence of events for active matrix interface timing is:
DIU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode,
DIU_CLK runs continuously. This signal frequency could be from 5 to 66 MHz depending on the panel type.
DIU_HSYNC causes the panel to start a new line. It always encompasses at least one DIU_CLK pulse.
DIU_VSYNC causes the panel to start a new frame. It always encompasses at least one DIU_HSYNC pulse.
DIU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display.
When disabled, the data is invalid and the trace is off.
Figure 33. Interface Timing Diagram for TFT LCD Panels
4.3.11.2
Interface to TFT LCD Panels, Electrical Characteristics
Figure 34 depicts the horizontal timing (timing of one line), including the horizontal sync pulse and the data. All parameters
shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DIU_CLK signal
(meaning the data and sync signals change at its rising edge) and active-high polarity of the DIU_HSYNC, DIU_VSYNC, and
DIU_DE signal. Signal polarity of DIU_HSYNC and DIU_VSYNC are selectable via the SYN_POL register, whether
active-high or active-low. The default is active-high. The DIU_DE signal is always active-high. Also, pixel clock inversion and
a flexible programmable pixel clock delay are also supported, programmed via the DIU Clock Config register (DCCR) in the
system clock module.
NOTES:
1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2 In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz.
3 In normal data transfer mode for MMC card, clock frequency can be any value between 0–20 MHz.
4 In card identification mode, card clock must be 100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.6 V.
5 Suggested Clock Period = T, CLK_DIVIDER (in SDHC Clock Rate register) = D, then TH = [(D + 1)/2] / (D + 1)
× T where [] is
round.
DIU_LD[23:0]
DIU_CLK
DIU_DE
DIU_HSYNC
DIU_VSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
12
3
m-1
m
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC5125YVN400 | 功能描述:微处理器 - MPU POWERPC EMBEDDED SOC SOC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC5125YVN400 | 制造商:Freescale Semiconductor 功能描述:ICMICROPROCESSOR32-BITCMOSPBGA324PI |
| MPC5125YVN400R | 制造商:Freescale Semiconductor 功能描述:POWERPC EMBEDDED SOC - Tape and Reel |
| MPC5200 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Hardware Specifications |
| MPC5200B | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:SDRAM/DDR Memory Controller |
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