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参数资料
| 型号： | MPC5554EVBE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 33/58页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR MPC5554 |
| 产品培训模块： | MPC55xx PitchPak Family |
| 标准包装： | 1 |
| 系列： | Qorivva |
| 类型： | MCU |
| 适用于相关产品： | MPC5554 |
| 所含物品： | 评估板和演示软件 |
| 配用： | MFR4310FRDC-ND - FRDC FLEXRAY DAUGHTER CARD |
| 相关产品： | MPC5554MZP132R2-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554MZP132-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554MVR132R2-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554MVR132-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554AZP132-ND - IC MPU 2M FLASH 132MHZ 416-PBGA |
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Electrical Characteristics
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
39
9
Data setup time for inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
tSUI
20
2
–4
20
—
20
2
3
20
—
20
2
6
20
—
ns
10
Data hold time for inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
tHI
–4
7
21
–4
—
–4
7
14
–4
—
–4
7
12
–4
—
ns
11
Data valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tSUO
—
5
25
18
5
—
5
25
14
5
—
5
25
13
5
ns
12
Data hold time for outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tHO
–5
5.5
8
–5
—
–5
5.5
4
–5
—
–5
5.5
3
–5
—
ns
1 All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types
of S or SH have an additional delay based on the slew rate. DSPI timing is specified at: VDDEH = 3.0–5.25 V;TA = TL to TH;
and CL = 50 pF with SRC = 0b11.
2 Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).
82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and
132 MHz parts allow for 128 MHz system clock + 2% FM.
3 The minimum SCK cycle time restricts the baud rate selection for the given system clock rate.
These numbers are calculated based on two MPC55xx devices communicating over a DSPI link.
4 The actual minimum SCK cycle time is limited by pad performance.
5 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
6 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
7 This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10.
Table 26. DSPI Timing1’ 2 (continued)
Spec
Characteristic
Symbol
80 MHz
112 MHz
132 MHz
Unit
Min.
Max.
Min.
Max.
Min.
Max.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC5554EVBE | 制造商:Freescale Semiconductor 功能描述:MPC5554 CUSTOMER DEMO BD |
| MPC5554EVBGHS | 功能描述:开发软件 GREEN HILLS SW Qorivva RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| MPC5554EVBISYS | 功能描述:开发软件 ISYSTEMS CONTENT Qorivva RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| MPC5554FS | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Qorivva MPC5554 Family |
| MPC5554INT | 功能描述:开发板和工具包 - 其他处理器 MPC5554 CUST. DEMO Qorivva RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
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