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| 型号： | MPC5554EVBE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 52/58页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR MPC5554 |
| 产品培训模块： | MPC55xx PitchPak Family |
| 标准包装： | 1 |
| 系列： | Qorivva |
| 类型： | MCU |
| 适用于相关产品： | MPC5554 |
| 所含物品： | 评估板和演示软件 |
| 配用： | MFR4310FRDC-ND - FRDC FLEXRAY DAUGHTER CARD |
| 相关产品： | MPC5554MZP132R2-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554MZP132-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554MVR132R2-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554MVR132-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554AZP132-ND - IC MPU 2M FLASH 132MHZ 416-PBGA |
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MPC5554 Microcontroller Data Sheet, Rev. 4
Revision History for the MPC5554 Data Sheet
Freescale Semiconductor
56
Table 20 (JTAG Pin AC Electrical Characteristics) JTAG Pin AC Electrical Characteristics
Footnote 1: Removed VDD = 1.35–1.65 V, and VDD33 and VDDSYN = 3.0–3.6 V.
Table 22 (Bus Operation Timing) Bus Operation Timing:
External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum
frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow
for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and 132 MHz parts
allow for 128 MHz system clock + 2% FM.
Specifications 5, 6, 7, and 8: Reordered the EBI signals within each specification.
Specifications 7 and 8: Removed EBI signals BDIP, OE, TSIZ[0:1], WE/BE[0:3].
Footnote 1: Removed VDD = 1.35–1.65 V, and VDD33 and VDDSYN = 3.0–3.6 V.
Footnote 8: Changed EBTS to SIU_ECCR[EBTS].
Table 23 (External Interrupt Timing) External Interrupt Timing (IRQ Signals)
Footnote 1: Removed VDD = 1.35–1.65 V; changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 24 (eTPU Timing) eTPU Timing
Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 25 (eMIOS Timing) eMIOS Timing
Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 26 (DSPI Timing’) DSPI Timing:
Footnote 1, changed ‘VDDEH = 3.0–5.5 V;’ to ‘VDDEH = 3.0–5.25 V;’
Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum
speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;
114 MHz parts allow for 112 MHz system clock + 2% FM; and 132 MHz parts allow for
128 MHz system clock + 2% FM.
Spec 1: SCK cycle time; Changed to 80 MHz minimum column from 25 to 24.4; 112 MHz minimum column from
17.9 to 17.5; 112 MHz maximum column from 2.0 to 2.1.
Table 27 (EQADC SSI Timing Characteristics) EQADC SSI Timing Characteristics
Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 28. Changes Between Rev. 2.0 and 3.0 (continued)
Location
Description of Changes
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC5554EVBE | 制造商:Freescale Semiconductor 功能描述:MPC5554 CUSTOMER DEMO BD |
| MPC5554EVBGHS | 功能描述:开发软件 GREEN HILLS SW Qorivva RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| MPC5554EVBISYS | 功能描述:开发软件 ISYSTEMS CONTENT Qorivva RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| MPC5554FS | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Qorivva MPC5554 Family |
| MPC5554INT | 功能描述:开发板和工具包 - 其他处理器 MPC5554 CUST. DEMO Qorivva RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
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