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| 型号： | MPC5566MZP132 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 52/66页 |
| 文件大小： | 0K |
| 描述： | MCU 3MB FLASH 132MHZ 416-PBGA |
| 标准包装： | 200 |
| 系列： | MPC55xx Qorivva |
| 核心处理器： | e200z6 |
| 芯体尺寸： | 32-位 |
| 速度： | 132MHz |
| 连通性： | CAN，EBI/EMI，以太网，SCI，SPI |
| 外围设备： | DMA，POR，PWM，WDT |
| 输入/输出数： | 256 |
| 程序存储器容量： | 3MB（3M x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 128K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 数据转换器： | A/D 40x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 416-BBGA |
| 包装： | 托盘 |
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MPC5566 Microcontroller Data Sheet, Rev. 3
Revision History for the MPC5566 Data Sheet
Freescale Semiconductor
56
Table 33. Changes Between Rev. 1.0 and 2.0
Location
Description of Changes
Table 3, MPC5566 Thermal Characteristics:
Changed for production purposes, footnote 1 from:
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
to:
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other board components, and board thermal
resistance.
Table 6, VCR/POR Electrical Specifications:
Added footnote 1 to specs 1, 2, and 3 that reads: On power up, assert RESET before VPOR15, VPOR33, and VPOR5
negate (internal POR). RESET must remain asserted until the power supplies are within the operating conditions
as specified in Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies fall
outside the operating conditions and until the internal POR asserts.
Table 9, DC Electrical Specifications:
Added footnote that reads: VDDE2 and VDDE3 are limited to 2.25–3.6 V only if EBTS = 0; VDDE2 and VDDE3 have
a range of 1.6–3.6 V if EBTS =1.
Removed footnote to specs 27a, b, and c on the max values that read: “Preliminary. Specification pending final
characterization.”
Removed footnote to specs 27a, b, and c on the max values that read: “Specification pending final
characterization.”
Table 16, Flash BIU Settings vs. Frequency of Operation:
Removed footnote 9 in columns APC and RWSC for 147 MHz row that read: Preliminary setting. Final setting
pending characterization.
Table 22, Bus Operation Timing:
External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum
frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow
for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM, 135 MHz parts allow
for 132 MHz system clock + 2% FM; and 147 MHz parts allow for 144 MHz system clock + 2% FM.
Spec 1: Changed the values in Min. columns: 40 MHz from 25 to 24.4; 56 MHz from 17.9 to 17.5
Specs 7 and 8: Removed from external bus interface: BDIP, OE, TSIZ[0:1], and WE/BE[0:3].
Table 26, DSPI Timing:
Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum
speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;
114 MHz parts allow for 112 MHz system clock + 2% FM, 135 MHz parts allow for 132 MHz system clock + 2%
FM; and 147 MHz parts allow for 144 MHz system clock + 2% FM.
Removed footnote that reads: “Specification pending final characterization.”
Spec 2, PCS to SCK delay, 144 MHz, min. 12
Spec 3, After SCK delay, 144 MHz, min. 11
Spec 9, Master (MTFE = 1, CPHA = 0), 144 MHz, min. 7
Spec 10, Master (MTFE = 1, CPHA = 0), 144 MHz, min. 11
Spec 11, Master (MTFE = 1, CPHA = 0), 144 MHz, max. 12
Spec 12, Master (MTFE = 1, CPHA = 0), 144 MHz, min. 1
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