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参数资料
| 型号： | MPC8306VMABDCA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 133 MHz, RISC PROCESSOR, PBGA369 |
| 封装： | 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369 |
| 文件页数： | 58/76页 |
| 文件大小： | 474K |
| 代理商： | MPC8306VMABDCA |
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MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
61
Clocking
22.1
System Clock Domains
As shown in Figure 42, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create four major clock domains:
The coherent system bus clock (csb_clk)
The QUICC Engine clock (qe_clk)
The internal clock for the DDR controller (ddr_clk)
The internal clock for the local bus controller (lbc_clk)
The csb_clk frequency is derived from the following equation:
csb_clk = SYS_CLK_IN × SPMF
Eqn. 1
The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the
csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers
are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is
loaded at power-on reset or by one of the hard-coded reset options.For more information, see the Reset
Configuration chapter in the MPC8306 PowerQUICC II Pro Communications Processor Reference
Manual.
The qe_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF])
and the QUICC Engine PLL division factor (RCWL[CEPDF]) as the following equation:
qe_clk = (QE_CLK_IN × CEPMF)
(1 + CEPDF)
Eqn. 2
qe_clk = (QE_CLK_IN × CEPMF)
(1 + CEPDF)
Eqn. 3
For more information, see the QUICC Engine PLL Multiplication Factor section and the “QUICC Engine
PLL Division Factor” section in the MPC8306 PowerQUICC II Pro Communications Processor
Reference Manual for more information.
The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(
2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCCR[CLKDIV].
For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8306 PowerQUICC
II Pro Communications Processor Reference Manual.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8306VMACDC | 制造商:Freescale Semiconductor 功能描述:MPC8306VMACDC - Bulk |
| MPC8306VMACDCA | 功能描述:微处理器 - MPU E300 MP 200 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8306VMADDC | 制造商:Freescale Semiconductor 功能描述:MPC8306VMADDC - Bulk |
| MPC8306VMADDCA | 功能描述:微处理器 - MPU E300 MP 266 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8306VMADDCA | 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 266 MHz 369-LFBGA |
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