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| 型号： | MPC8313ZQADD |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 87/99页 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC II PRO 516PBGA |
| 标准包装： | 40 |
| 系列： | MPC83xx |
| 处理器类型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 267MHz |
| 电压： | 0.95 V ~ 1.05 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 516-BBGA 裸露焊盘 |
| 供应商设备封装： | 516-PBGAPGE（27x27） |
| 包装： | 托盘 |
| 配用： | MPC8313E-RDB-ND - BOARD PROCESSOR |
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MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
88
Freescale Semiconductor
22.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,
AVDD2, and SDAVDD, respectively). The AVDD level should always be equivalent to VDD, and preferably
these voltages are derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits as illustrated in Figure 58, one to each of the five AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias.
This figure shows the PLL power supply filter circuits.
Figure 58. PLL Power Supply Filter Circuit
The SDAVDD signal provides power for the analog portions of the SerDes PLL. To ensure stability of the
internal clock, the power supplied to the PLL is filtered using a circuit like the one shown in Figure 59.
For maximum effectiveness, the filter circuit should be placed as closely as possible to the SDAVDD ball
to ensure it filters out as much noise as possible. The ground connection should be near the SDAVDD ball.
The 0.003-F capacitor is closest to the ball, followed by the two 2.2-F capacitors, and finally the 1-
resistor to the board supply plane. The capacitors are connected from traces from SDAVDD to the ground
plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be
kept short, wide, and direct.
Figure 59. SerDes PLL Power Supply Filter Circuit
Note the following:
SDAVDD should be a filtered version of XCOREVDD.
VDD
AVDD1 and AVDD2
10
2.2 F
Low ESL Surface Mount Capacitors
Note:
1. An 0805 sized capacitor is recommended for system initial bring-up.
XCOREVDD
SDAVDD
SDAVSS
2.2 F1
0.003 F
1.0
2.2 F1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8313ZQADDB | 功能描述:微处理器 - MPU REV2.1 W/OENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8313ZQADDC | 功能描述:微处理器 - MPU 8313 REV2.2 PB NO ENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8313ZQAFD | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8313ZQAFDA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8313ZQAFDB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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