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| 型号： | MPC8314VRADDA |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 64/101页 |
| 文件大小： | 0K |
| 描述： | MPU POWERQUICC II PRO 620-PBGA |
| 标准包装： | 36 |
| 系列： | MPC83xx |
| 处理器类型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 266MHz |
| 电压： | 1V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 620-BBGA 裸露焊盘 |
| 供应商设备封装： | 620-PBGA（29x29） |
| 包装： | 托盘 |
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MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
65
PCI Express
16.5
Receiver Compliance Eye Diagrams
The RX eye diagram in Figure 50 is specified using the passive compliance/test measurement load (see
Figure 51) in place of any real PCI Express RX component. In general, the minimum receiver eye diagram
measured with the compliance/test measurement load (see Figure 51) is larger than the minimum receiver
eye diagram measured over a range of systems at the input receiver of any real PCI Express component.
The degraded eye diagram at the input Receiver is due to traces internal to the package as well as silicon
parasitic characteristics which cause the real PCI Express component to vary in impedance from the
compliance/test measurement load. The input receiver eye diagram is implementation specific and is not
specified. RX component designer should provide additional margin to adequately compensate for the
degraded minimum Receiver eye diagram (shown in Figure 50) expected at the input receiver based on an
adequate combination of system simulations and the return loss measured looking into the RX package
and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the
eye diagram.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
UI.
NOTE
The reference impedance for return loss measurements is 50
to ground for
both the D+ and D- line (that is, as measured by a Vector Network Analyzer
with 50
probes—see Figure 51). Note that the series capacitors,
CPEACCTX, are optional for the return loss measurement.
Figure 50. Minimum Receiver Eye Timing and Voltage Compliance Specification
16.5.1
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within
0.2 inches of the package pins, into a test/measurement load shown in Figure 51.
VRX-DIFFp-p-MIN > 175 mV
0.4 UI = TRX-EYE-MIN
VRX-DIFF = 0 mV
(D+ D– Crossing Point)
VRX-DIFF = 0 mV
(D+ D– Crossing Point)
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| MPC8314VRAGDA | 功能描述:微处理器 - MPU NON-ENCRYPT RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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| MPC8315CVRADDA | 功能描述:微处理器 - MPU NON-ENCRYPT RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8315CVRAFDA | 功能描述:微处理器 - MPU NON-ENCRYPT RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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