参数资料
型号: MPC8314VRADDA
厂商: Freescale Semiconductor
文件页数: 85/101页
文件大小: 0K
描述: MPU POWERQUICC II PRO 620-PBGA
标准包装: 36
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 266MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 620-BBGA 裸露焊盘
供应商设备封装: 620-PBGA(29x29)
包装: 托盘
MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
84
Freescale Semiconductor
Package and Pin Listings
VDD
J15, K15, K16, K17, K18, K19, L10, L19,
M10, T10, U10, U19, V10, V19, W11, W12,
W13, W14, W15, W16, W17, W18, P23,
R23, T19, M26, N26, P28, R28, U23, N27
I—
VDDC
J14, K11, K12, K13,
K14, M19
I—
VSS
A3, A27, B3, B12, B24, B28, C6, C8, C13,
C17, C21, C23, C26, D2, D7, D15, D18,
D20, D22, E4, E6, E11, E24, E26, F8, F12,
F14, F17, F20, G3, G26, H4, H23, J6, J26,
K25, L4, L11, L12, L13, L14, L15, L16, L17,
L18, L23, L28, M3, M11, M12, M13, M14,
M15, M16, M17, M18, N5, N11, N12, N13,
N14, N15, N16, N17, N18, P6, P11, P12,
P13, P14, P15, P16, P17, P18, R6, R11,
R12, R13, R14, R15, R16, R17, R18, T11,
T12, T13, T14, T15, T16, T17, T18, U5, U6,
U11, U12, U13, U14, U15, U16, U17, U18,
V6, V11, V12, V13, V14, V15, V16, V17,
V18, W5, W25, W27, Y2, Y23, AA6, AA27,
AB2, AB26, AC5, AC9, AC12, AC18, AC21,
AD3, AD14, AD16, AD20, AD26, AE2,
AE7, AE11, AE16, AE22, AE24, AF2, AF9,
AF12, AF18, AF20, AF23, AF27, AG1,
AG5, AG11, AG16, AG22, AG28, AH27,
U28,N28, M28, T28, V27, M27, V28, T26,
P24, R19, R20, R24, M24, N24, P19, P20,
P25, P27, R25, R27, T24
I—
XCOREVDD
P2, P10, R2, T1
I
XCOREVSS
R3, R10, U2, V2
I
XPADVDD
P3, R9, U3
I
XPADVSS
P5, P9, V3
I
Note:
1. This pin is an open drain signal. A weak pull-up resistor (1 k
) should be placed on this pin to NVDD.
2. This pin is an open drain signal. A weak pull-up resistor (2–10 k
) should be placed on this pin to NVDD.
3. This output is actively driven during reset rather than being three-stated during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.
6. This pin must always be tied to VSS.
7. Thermal sensitive resistor.
8. This pin should be
connected to USB_VSSA_BIAS through 10K precision resistor.
9. The LB_POR_CFG_BOOT_ECC functionality for this pin is only available in MPC8314E revision 1.1 and later. The
LB_POR_CFG_BOOT_ECC is sampled only during the PORESET negation. This pin with an internal pull down resistor enables
the ECC by default. To disable the ECC an external strong pull up resistor or a tristate buffer is needed.
10.This pin has a weak internal pull-down.
11.This pin has a weak internal pull-up.
Table 66. MPC8314E TEPBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Note
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