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参数资料
型号： MPC8377EVRAGDA
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封装： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件页数： 50/124页
文件大小： 1462K
代理商： MPC8377EVRAGDA
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
31
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.3.2
MII Management AC Electrical Specifications
Table 32 provides the MII management AC timing specifications.
Table 31. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter
Conditions
Symbol
Min
Max
Unit
Supply voltage (3.3 V)
—
LVDD1
3.135
3.465
V
Output high voltage
IOH = –1.0 mA
LVDD1 = Min
VOH
2.10
LVDD1 +0.3
V
Output low voltage
IOL = 1.0 mA
LVDD1 = Min
VOL
GND
0.50
V
Input high voltage
—
VIH
2.00
—
V
Input low voltage
—
VIL
—0.80
V
Input high current
LVDD1 = Max
VIN
1 = 2.1 V
IIH
—30
μA
Input low current
LVDD1 = Max
VIN = 0.5 V
IIL
–600
—
μA
Table 32. MII Management AC Timing Specifications
Parameter
Symbol 1
Min
Typical
Max
Unit
Notes
MDC frequency
fMDC
2.5
—
8.3
MHz
2, 3
MDC period
tMDC
80
—
400
ns
—
MDC clock pulse width high
tMDCH
32
—
ns
—
MDC to MDIO valid
tMDKHDV
2
× (tplb_clk × 8)
—
ns
5
MDC to MDIO delay
tMDKHDX
10
—
2
× (tplb_clk × 8)
ns
3, 5
MDIO to MDC setup time
tMDDVKH
5—
—
ns
—
MDIO to MDC hold time
tMDDXKH
0—
—
ns
—
MDC rise time
tMDCR
——
10
ns
4
MDC fall time
tMDCF
——
10
ns
4
Note:
1 The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data
hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the
valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
2 This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency
divided by 64.)
3 This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency
is 8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz and
the minimum frequency is 1.7 MHz.)
4 Guaranteed by design.
5 t
plb_clk is the platform (CSB) clock divided according to the SCCR[TSEC1CM].
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