- 您现在的位置：买卖IC网 > PDF目录80409 > MPC8377EVRAGDA (FREESCALE SEMICONDUCTOR INC) 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689 PDF资料下载
参数资料
| 型号： | MPC8377EVRAGDA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689 |
| 封装： | 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689 |
| 文件页数： | 84/124页 |
| 文件大小： | 1462K |
| 代理商： | MPC8377EVRAGDA |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页当前第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
62
Freescale Semiconductor
PCI Express
15.4.2
Transmitter Compliance Eye Diagrams
The Tx eye diagram in Figure 42 is specified using the passive compliance/test measurement load (see
Figure 44) in place of any real PCI Express interconnect + Rx component. There are two eye diagrams that
must be met for the transmitter. Both diagrams must be aligned in time using the jitter median to locate the
center of the eye diagram. The different eye diagrams differ in voltage depending on whether it is a
Common mode return
loss
Measured over 50 MHz to
1.25 GHz.
RLTX-CM
6—
—
dB
DC differential Tx
impedance
Tx DC differential mode low
impedance
ZTX-DIFF-DC
80
100
120
Ω
—
Transmitter DC
impedance
Required Tx D+ as well as D–
DC impedance during all
states
ZTX-DC
40
—
Ω
—
Lane-to-Lane output
skew
Static skew between any two
transmitter lanes within a
single link
LTX-SKEW
—
500 +
2UI
ps
—
AC coupling capacitor
All transmitters should be AC
coupled. The AC coupling is
required either within the
media or within the
transmitting component itself.
CTX
75
—
200
nF
—
Crosslink random
timeout
This random timeout helps
resolve conflicts in crosslink
configuration by eventually
resulting in only one
downstream and one
upstream port.
Tcrosslink
0—
1
ms
Note:
1 No test load is necessarily associated with this value.
2 Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 44 and measured over
any 250 consecutive Tx UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 42.)
3 A T
TX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the
transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total
Tx jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed
to the averaged time value.
4 The transmitter input impedance will result in a differential return loss greater than or equal to 12 dB and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50
Ω to ground for both the D+ and
D– line (that is, as measured by a vector network analyzer with 50-
Ω probes, see Figure 44). Note that the series capacitors,
CTX, is optional for the return loss measurement.
5 Measured between 20%–80% at transmitter package pins into a test load as shown in Figure 44 for both V
TX-D+ and VTX-D-.
6 See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a.
7 See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a.
Table 51. Differential Transmitter (Tx) Output Specifications (continued)
Parameter
Conditions
Symbol
Min
Typical
Max
Units
Notes
相关PDF资料 |
PDF描述 |
|---|---|
| MC9S12XEP100VAG | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP144 |
| MC9S12XEP768MAG | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP144 |
| MC7448VU1250NC | 32-BIT, 1250 MHz, RISC PROCESSOR, CBGA360 |
| MPC8541CPXAQDX | 32-BIT, 1600 MHz, RISC PROCESSOR, CBGA360 |
| MPC8541CVTAJDX | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA360 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8377EVRAGFA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8377EVRAGGA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8377EVRAJDA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8377EVRAJF | 功能描述:微处理器 - MPU PBGA W/ ENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8377EVRAJFA | 功能描述:微处理器 - MPU 8377 PBGA ST PbFr W/ENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
发布紧急采购，3分钟左右您将得到回复。