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参数资料
型号： MPC8378ECVRAJDA
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封装： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件页数： 59/125页
文件大小： 894K
代理商： MPC8378ECVRAJDA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
39
9USB
This section provides the AC and DC electrical characteristics for the USB dual-role controllers.
9.1
USB DC Electrical Characteristics
This table provides the DC electrical characteristics for the ULPI interface at recommended OVDD =3.3 V±165 mV.
9.2
USB AC Electrical Specifications
This table describes the general timing parameters of the USB interface of the device.
Table 39. USB DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Note
High-level input voltage
VIH
2OVDD + 0.3
V
1
Low-level input voltage
VIL
–0.3
0.8
V
1
Input current
IIN
—±30
A
2
High-level output voltage, IOH = –100 AVOH
OVDD – 0.2
—
V
—
Low-level output voltage, IOL = 100 AVOL
—0.2
V
—
Notes:
1. The minimum VIL and maximum VIH values are based on the respective minimum and maximum OVIN values found in
Table 3.
2. The symbol OVIN represents the input voltage of the supply and is referenced in Table 3.
Table 40. USB General Timing Parameters (ULPI Mode Only)
Parameter
Symbol 1
Min
Max
Unit
Note
USB clock cycle time
tUSCK
15
—
ns
2, 3, 4, 5
Input setup to USB clock—all inputs
tUSIVKH
4—
ns
2, 3, 4, 5
Input hold to USB clock—all inputs
tUSIXKH
1—
ns
2, 3, 4, 5
USB clock to output valid—all outputs
tUSKHOV
—7
ns
2, 3, 4, 5
Output hold from USB clock—all outputs
tUSKHOX
2—
ns
2, 3, 4, 5
Notes:
1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US) for
the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes
USB timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold
time.
2. All timings are in reference to the USB clock, USBDR_CLK.
3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.4 OVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered through
the component pin is less than or equal to that of the leakage current specification.
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