参数资料
型号: MPC8378ECVRAJDA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封装: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件页数: 92/125页
文件大小: 894K
代理商: MPC8378ECVRAJDA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
69
15.4.2
Transmitter Compliance Eye Diagrams
The Tx eye diagram in Figure 46 is specified using the passive compliance/test measurement load (see Figure 48) in place of
any real PCI Express interconnect + Rx component. There are two eye diagrams that must be met for the transmitter. Both
diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. The different eye diagrams
differ in voltage depending on whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level of the
de-emphasized bit is always relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
Common mode return
loss
Measured over 50 MHz to
1.25 GHz.
RLTX-CM
6—
dB
4
DC differential Tx
impedance
Tx DC differential mode low
impedance
ZTX-DIFF-DC
80
100
120
Transmitter DC
impedance
Required Tx D+ as well as D–
DC impedance during all
states
ZTX-DC
40
Lane-to-Lane output
skew
Static skew between any two
transmitter lanes within a
single link
LTX-SKEW
500 +
2UI
ps
AC coupling capacitor
All transmitters should be AC
coupled. The AC coupling is
required either within the
media or within the
transmitting component itself.
CTX
75
200
nF
Crosslink random
timeout
This random timeout helps
resolve conflicts in crosslink
configuration by eventually
resulting in only one
downstream and one
upstream port.
Tcrosslink
0—1
ms
7
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 48 and measured
over any 250 consecutive Tx UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 46.)
3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the
transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total
Tx jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
4. The transmitter input impedance will result in a differential return loss greater than or equal to 12 dB and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50
to ground for both the D+
and D– line (that is, as measured by a vector network analyzer with 50-
probes, see Figure 48). Note that the series
capacitors, CTX, is optional for the return loss measurement.
5. Measured between 20%–80% at transmitter package pins into a test load as shown in Figure 48 for both VTX-D+ and VTX-D-.
6. See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a.
7. See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a.
Table 57. Differential Transmitter (Tx) Output Specifications (continued)
Parameter
Conditions
Symbol
Min
Typical
Max
Units
Note
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