参数资料
型号: MPC8378ECVRAJDA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封装: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件页数: 87/125页
文件大小: 894K
代理商: MPC8378ECVRAJDA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
64
The following table shows the PCI AC timing specifications at 33 MHz.
Input hold from cock
tPCIXKH
0.25
ns
Output clock skew
tPCKOSK
—0.5
ns
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN
clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to
the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. PCI specifications allows 1 ns skew for 66 MHz but includes the total allowed skew, board, connectors, etc.
6. Value does not comply with the PCI 2.3 Local Bus Specifications.
Table 55. PCI AC Timing Specifications at 33 MHz
PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1
OV
DD, VIH = 0.7 OVDD.
Parameter
Symbol1
Min
Max
Unit
Note
Clock to output valid
tPCKHOV
—11
ns
Output hold from clock
tPCKHOX
2—
ns
Clock to output high impedance
tPCKHOZ
—14
ns
2, 3
Input setup to clock
tPCIVKH
3.0
ns
2, 4
Input hold from clock
tPCIXKH
0.25
ns
Output clock skew
tPCKOSK
—0.5
ns
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the
PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC)
with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. PCI specifications allows 2 ns skew for 33 MHz but includes the total allowed skew, board, connectors, etc.
6. Value does not comply with the PCI 2.3 Local Bus Specifications.
Table 54. PCI AC Timing Specifications at 66 MHz (continued)
PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1
OV
DD, VIH = 0.7 OVDD.
Parameter
Symbol1
Min
Max
Unit
Note
相关PDF资料
PDF描述
MPC8378EVRALFA 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
MPC8378VRAJGA 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
MPC8378CVRANFA 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
MPC8378VRALFA 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
MPC8378CVRAGGA 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
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