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参数资料
| 型号： | MPC8560VT667LC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 14/36页 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC III 783-FCPBGA |
| 标准包装： | 36 |
| 系列： | MPC85xx |
| 处理器类型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 667MHz |
| 电压： | 1.2V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 784-BBGA，FCBGA |
| 供应商设备封装： | 783-FCPBGA（29x29） |
| 包装： | 托盘 |
| 配用： | MPC8560ADS-BGA-ND - BOARD APPLICATION DEV 8560 |
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MOTOROLA
MPC8560 PowerQUICC III
21
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Data Processing with the e500 Coherency Module
programmed destination of the transaction. The following is a general overview of how the ATMUs process
transactions over the on-chip fabric. (Refer to Figure 4.)
1. When a transaction on one of the fabric ports begins, the ATMU on the origination port translates
the programmed destination address into both a destination fabric port ID and a local device
address.
2. The data is then processed across the on-chip fabric from the origination port to the destination
port.
3. If the destination port connects off-chip (for example, to a PCI or RapidIO device), the local
device address is translated by the destination port ATMU to an outbound address with respect to
the destination port’s memory map, and the data is processed accordingly.
Figure 4. Processing Transactions Across the On-Chip Fabric
4.3
Data Processing with the e500 Coherency Module
Processing through the ECM is similar to processing between the CPM and local bus or across the on-chip
fabric (in the sense of how data is received and transmitted) with the exception that the transaction passes
through the ECM. The purpose of the ECM is to provide a means for any I/O transaction to maintain
coherency with the cacheable DDR SDRAM and the local bus memory (except in the case where the CPM
is directly accessing the local bus). However, simply using the ECM does not make transactions across it
coherent. The e500 and L2 cache are snooped to maintain coherency only if the transaction across the ECM
is designated as global (GBL bit set). Otherwise, the transaction passes through the ECM using the ECM as
a simple conduit to get to its destination. In essence, only global transactions across the ECM are coherent
transactions; all other transaction (between the CPM and the local bus and across the on-chip fabric) are
non-coherent.
Although transactions between the CPM and local bus are considered non-coherent because the CPM
typically interfaces directly to the local bus (where its buffers are stored), CPM transactions can be made
coherent. ATM transactions on a per-connection and direction basis can be set as coherent by setting the
necessary bits in the receive and transmit connection tables. Coherency of MCC transactions per logical
channel is determined by bits set in TSTATE. FCC and SCC transactions per physical channel and direction
can be programmed as coherent by setting the appropriate bits in the FCC and SCC functional code
registers, respectively.
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