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参数资料
| 型号： | MPC8560VT667LC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 23/36页 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC III 783-FCPBGA |
| 标准包装： | 36 |
| 系列： | MPC85xx |
| 处理器类型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 667MHz |
| 电压： | 1.2V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 784-BBGA，FCBGA |
| 供应商设备封装： | 783-FCPBGA（29x29） |
| 包装： | 托盘 |
| 配用： | MPC8560ADS-BGA-ND - BOARD APPLICATION DEV 8560 |
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MOTOROLA
MPC8560 PowerQUICC III
3
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Key Features
— The single-precision floating-point (SPFP) APU provides an instruction set for single-precision
(32-bit) floating-point instructions.
— Memory management unit (MMU) especially designed for embedded applications
— Enhanced hardware and software debug support
— Performance monitor facility (similar to but different from the MPC8560 performance monitor
described in the MPC8560 PowerQUICC III Integrated Communications Processor Reference
Manual.)
The e500 defines features that are not implemented on the MPC8560. It also generally defines some
features that the MPC8560 implements more specifically. An understanding of these differences
can be critical to ensure proper operation. These differences are summarized in Section 5.14,
“MPC8560 Implementation Details,” in the reference manual.
Section 3.1, “e500 Core Overview,” in the reference manual includes a comprehensive list of e500
core features.
High-performance RISC CPM operating at up to 333 MHz
— CPM software compatibility with previous PowerQUICC families
— One instruction per clock
— Executes code from internal ROM or instruction RAM
— 32-bit RISC architecture
— Tuned for communication environments—Instruction set supports CRC computation and bit
manipulation
— Internal timer
— Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and
virtual DMA channels for each peripheral controller
— Handles serial protocols and virtual DMA
— Three full-duplex fast serial communications controllers (FCCs) that support the following
protocols:
– ATM protocol through UTOPIA interface (FCC1 and FCC2 only)
– IEEE802.3/fast Ethernet
– HDLC
– Totally transparent operation
— Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent
channels at 64 Kbps each, multiplexed on up to 8 TDM interfaces
— Four full-duplex serial communications controllers (SCCs) that support the following
protocols:
– High level/synchronous data link control (HDLC/SDLC)
– LocalTalk (HDLC-based local area network protocol)
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART (1x clock mode)
– Binary synchronous communication (BISYNC)
– Totally transparent operation
— Serial peripheral interface (SPI) support for master or slave
—I2C bus controller
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For More Information On This Product,
Go to: www.freescale.com
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