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参数资料
| 型号： | MPC8560VT667LC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 6/36页 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC III 783-FCPBGA |
| 标准包装： | 36 |
| 系列： | MPC85xx |
| 处理器类型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 667MHz |
| 电压： | 1.2V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 784-BBGA，FCBGA |
| 供应商设备封装： | 783-FCPBGA（29x29） |
| 包装： | 托盘 |
| 配用： | MPC8560ADS-BGA-ND - BOARD APPLICATION DEV 8560 |
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14
MPC8560 PowerQUICC III
MOTOROLA
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
e500 Coherency Module (ECM)
— Locks for the entire cache may be set and cleared by accesses to memory-mapped control
registers
3.3.1
On-Chip Memory as Memory-Mapped SRAM
When the on-chip memory is configured as an SRAM, the 256 Kbytes of memory can be configured to
reside at any aligned location in the memory map. It is byte-accessible and fully ECC-protected, using
read-modify-write transactions for sub-cacheline transactions. I/O devices can access the SRAM by
marking transactions global so that they are directed to the CCB.
3.3.2
On-Chip Memory as L2 Cache
The MPC8560 on-chip memory arrays include a 256-Kbyte data array, an address tag array, and a status
array.
The data array is organized as 1024 sets of 8 cache lines. Each cache line size is 32 bytes. The replacement
policy in each eight-way set is governed by a pseudo-LRU algorithm. The data is protected with ECC, and
the tag array is protected by parity.
The L2 cache tags are non-blocking for efficient load/store and snooping operations. The L2 cache can be
accessed internally while a load miss is pending (allowing hits under misses). Subsequent to a load miss
updating the memory, loads or stores can occur to that line on the very next cycle.
The L2 status array maintains status bits for each line to determine the status of the line. Different
combinations of these bits result in different L2 states. Note that because the cache is always write-through,
there is no modified state. The status bits include the following:
V—Valid
IL—Instruction locked
DL—Data locked
All accesses to the L2 memory are fully pipelined so back-to-back loads and stores can have single-cycle
throughput.
The cache can be configured to allocate instructions-only, data-only, or both. It can also be configured to
allocate global I/O writes that correspond to a programmable address window or that use a special
transaction type (stashing). In this way, DMA engines or I/O devices can force data into the cache.
Line locks can be set in a variety of ways. The Book E architecture defines instructions that explicitly set
and clear locks in the L2. These instructions are supported by the core complex and the L2 controller. In
addition, the L2 controller can be configured to lock all lines that fall into either of two specified address
ranges when the line is allocated. Finally, the entire cache can be locked by writing to a configuration
register in the L2 cache controller.
The status array tracks line locks as either instruction locks or data locks for each line, and the status array
supports flash clearing of all instruction locks or data locks separately by writes to configuration registers
in the L2 controller.
3.4
e500 Coherency Module (ECM)
The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop the bus
between the e500 core and the integrated L2 cache in order to maintain coherency across local cacheable
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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