参数资料
型号: MPC8572CLVTAULD
厂商: Freescale Semiconductor
文件页数: 92/138页
文件大小: 0K
描述: MPU POWERQUICC III 1023-PBGA
标准包装: 1
系列: MPC85xx
处理器类型: 32-位 MPC85xx PowerQUICC III
速度: 1.333GHz
电压: 1.1V
安装类型: 表面贴装
封装/外壳: 1023-BBGA,FCBGA
供应商设备封装: 1023-FCPBGA(33x33)
包装: 托盘
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
57
Local Bus Controller (eLBC)
Figure 29 provides the AC test load for the local bus.
Figure 29. Local Bus AC Test Load
Local bus clock to output valid (except LAD/LDP and
LALE)
tLBKHOV1
—3.2
ns
Local bus clock to data valid for LAD/LDP
tLBKHOV2
—3.2
ns
3
Local bus clock to address valid for LAD
tLBKHOV3
—3.2
ns
3
Local bus clock to LALE assertion
tLBKHOV4
—3.2
ns
3
Output hold from local bus clock (except LAD/LDP and
LALE)
tLBKHOX1
0.9
ns
3
Output hold from local bus clock for LAD/LDP
tLBKHOX2
0.9
ns
3
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
tLBKHOZ1
—2.6
ns
5
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ2
—2.6
ns
5
Note:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock
reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the
tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus
clock for PLL bypass mode to 0.4
× BVDD of the signal in question for 1.8-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT
is programmed with the LBCR[AHD] parameter.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured
between complementary signals at BVDD/2.
8. Guaranteed by design.
Table 51. Local Bus General Timing Parameters (BVDD = 1.8 V DC)—PLL Enabled (continued)
At recommended operating conditions with BVDD of 1.8 V ± 5% (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
BVDD/2
RL = 50 Ω
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